Pronesis Technologies

Company Description Pronesis partners with leading technology companies globally to offer world-class solutions. The company specializes in a variety of engineering services including ASIC/VLSI design, embedded product development, and product engineering. Whether it’s SoC verification, hardware design and testing, or product support, Pronesis ensures top-tier service in every domain. What You’ll Be Doing: Lead block/chip level Physical Design (PD) activities , including floor planning, abstract view generation, RC extraction, PNR, STA, EM/IR drop, DRCs, and schematic-to-layout verification. Collaborate with RTL/design teams to solve complex design challenges and optimize PPA . Debug tool/design issues and improve RTL2GDSII flows for better efficiency. Handle full-cycle PD tasks for GPU and other ASICs. Drive block-level and full-chip floor-planning, timing closure, and physical verification . Collaborate with RTL design, verification, and DFT teams to ensure high design quality and robustness. Develop and implement physical design methodologies and best practices to enhance design efficiency and quality. What We’re Looking For: BE/BTech/MTech in Electronics/Electrical Engineering or equivalent experience. 4–8 years of experience in Physical Design. Strong understanding of RTL2GDSII flow, synthesis, place & route, CTS, STA, timing convergence, and layout closure . Hands-on experience with Cadence Innovus, Synopsys ICC2/PrimeTime/Tempus or equivalent PD tools. Expertise in high-frequency design methodologies and advanced technology nodes up to 2nm . Proficient in Perl, Tcl, Python, and tool-specific scripting for automation. Knowledge of Verilog/VHDL and digital logic design. Strong analytical, problem-solving, and communication skills with the ability to work in a global, collaborative environment. Locations: Ahmedabad & Bangalore.