Hiring VLSI Engineers with 3-12 yrs experience in RTL Design/Verification, STA, DFT, PD, or Analog/Mixed-Signal. Strong Verilog/SV, Spice, Python/TCL scripting, and EDA tool expertise required. Immediate joiners preferred. Multiple openings
Hiring VLSI Engineers with 3-12 yrs experience in RTL Design/Verification, STA, DFT, PD, or Analog/Mixed-Signal. Strong Verilog/SV, Spice, Python/TCL scripting, and EDA tool expertise required. Immediate joiners preferred. Multiple openings