Multimedia Core IP RTL Design Engineer, Silicon

**Role Overview:** You will be part of a team that pushes boundaries by developing custom silicon solutions for Google's direct-to-consumer products. Your role will contribute to the innovation behind products loved by millions worldwide, shaping the next generation of hardware experiences with unparalleled performance, efficiency, and integration. **Key Responsibilities:** - Collaborate with architects to develop microarchitecture. - Perform Verilog/SystemVerilog RTL coding, functional/performance simulation debug, and Lint/CDC/FV/UPF checks. - Develop RTL implementations meeting power, performance, and area goals. - Participate in synthesis, timing/power closure, and support pre-silicon and post-silicon bring-up. - Travel to collaborate with global teams at other sites across the world. **Qualifications Required:** - Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science with a focus on computer architecture, or equivalent practical experience. - 4 years of experience in RTL coding. - Experience with methodologies for RTL quality checks such as Lint, CDC, RDC. **Additional Details:** The gChips team at Google develops custom silicon solutions for Google Hardware products, aiming to provide differentiated user experiences and optimize performance and power for specific use cases. This involves designing SoCs and other integrated circuits. Working closely with various teams within Google, gChips ensures that the hardware product area is informed about the latest chip technologies and standards for CPU, IO, and memory.,