Sr Staff Engineer, STA & PNR Renesas Electronics

10.0 - 14.0 years

0 Lacs

hyderabad, telangana

On-site

You will be responsible for leading Static Timing Analysis (STA) and Place and Route (PNR) activities for complex subsystems within ASIC/SoC design. Your focus will be on achieving robust timing closure and optimizing physical implementation in terms of power, performance, and area. Your role will involve developing and refining methodologies for STA and PNR specifically tailored to address the challenges posed by large, multi-interface, or mixed-signal subsystems. You will drive automation and validation of timing and physical design data across subsystem boundaries to ensure seamless integration. As a key member of the team, you will mentor and guide junior engineers, fostering their technical growth and promoting knowledge sharing within subsystem teams. Collaboration across functions to address design, timing, and physical implementation challenges unique to complex subsystem integration will be a crucial aspect of your responsibilities. Your excellent communication skills will be essential for presenting technical solutions and leading discussions with internal teams and customers, especially in relation to subsystem-level trade-offs and integration. To be successful in this role, you should have at least 10 years of experience in STA and PNR for complex subsystems within ASIC/SoC design, including expertise in advanced technology nodes (7nm or below). Proficiency in tools such as Synopsys PrimeTime, Cadence Tempus for STA, and Synopsys ICC2, Cadence Innovus for PNR applied to large, multi-block, or hierarchical subsystems is required. Experience in timing closure, floorplanning, placement, clock tree synthesis, routing, and physical verification for high-complexity subsystems is essential. Additionally, you should be proficient in scripting languages (Tcl, Perl, Python) for automating STA and PNR flows across multiple subsystem blocks. A deep understanding of SoC design flows and experience collaborating across frontend, physical design, and verification teams to integrate complex subsystems will be advantageous. Background knowledge in high-speed interfaces or mixed-signal SoC subsystems is preferred. Join Renesas to be a part of a global team dedicated to building a sustainable future where technology enhances lives and shapes the world of electronics. Let's shape the future together at Renesas.,

Posted 1 week ago

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