2.0 - 7.0 years

0 Lacs

karnataka

On-site

As an experienced ASIC design engineer at Qualcomm India Private Limited, you will be responsible for micro-architecture development, RTL design, and front-end flows. Your key responsibilities will include: - Mirco architecture & RTL development and its validation for linting, clock-domain crossing, and DFT rules. - Working with the functional verification team on test-plan development and waveform debugs at core, sub-system, SoCs levels. - Hands-on experience in constraint development and timing closure. - UPF writing, power-aware equivalence checks, and low power checks. - Supporting performance debugs and addressing performance bottlenecks. - Providing support to sub-system, SoC integrati...

Posted 3 weeks ago

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RTL Design Engineer-Staff Qualcomm

2.0 - 7.0 years

0 Lacs

karnataka

On-site

As an experienced ASIC design engineer at Qualcomm India Private Limited, you will be responsible for the micro-architecture development, RTL design, and validation for linting, clock-domain crossing, and DFT rules. Your expertise will be utilized in working with the functional verification team on test-plan development and waveform debugs at core, sub-system, and SoCs levels. Additionally, you will play a crucial role in constraint development, timing closure, UPF writing, power-aware equivalence checks, and low power checks. Your support will be vital in performance debugs and addressing performance bottlenecks, as well as providing assistance to sub-system, SoC integration, and chip level...

Posted 3 weeks ago

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ASIC/RTL Design Engineer(DDR)- Staff Qualcomm

2.0 - 7.0 years

0 Lacs

karnataka

On-site

Qualcomm India Private Limited is looking for an experienced ASIC Design Engineer to join their Engineering Group, Hardware Engineering division. As an ideal candidate, you should hold an MTech/BTech in EE/CS with a minimum of 7 years of experience in ASIC design. Your responsibilities will include micro-architecture development, RTL design, front-end flows, synthesis, DFT, FV, and STA. A good understanding of DDR families and generations, as well as protocols like AHB/AXI/ACE/CHI, will be advantageous. Experience with post-silicon bring-up and debug is a plus. You should be able to collaborate effectively with global teams and possess strong communication skills. Hands-on experience in Mult...

Posted 3 months ago

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