3 Mcmm Jobs

Alternate Job Titles: ASIC Physical Design Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly motivated and experienced Physical Design Engineer with a passion for implementing and performing signoff verifications of digital blocks using ASIC design flow (Gate2GDSII). You thrive in dynamic environments and have a knack for problem-solving and innovation. Your expertise in digital block implementation, from gate netlist to GDSII, is complemented by your hands-on experience with state-of-the-art ASIC flows. You understand the intricacies of design initialization, power planning, floor planning/macro placement, scan-chain reordering, CTS, route, and chip finishing steps. You have a solid foundation in physical implementation, signoff verifications (DRC, LVS, Antenna), and reliability verifications (EMIR, ESD). Your ownership of writing MCMM and UPF for block designs showcases your leadership and technical prowess. You are adept at providing handoff data to other signoff closure like STA, formality, layout, and reliability verification. With a minimum of 5 years of relevant experience in the physical design domain and a B.E/B.Tech/M.Tech in ECE/EE, you are ready to take on new challenges and contribute to groundbreaking projects. What Youll Be Doing: Implementing digital blocks using state-of-the-art gate to GDSII ASIC flows. Performing physical implementation of blocks from gate netlist to GDSII. Conducting signoff verifications, including layout verifications (DRC, LVS, Antenna) and reliability verifications (EMIR, ESD). Writing MCMM and UPF for block designs. Providing handoff data for other signoff closure processes like STA, formality, layout, and reliability verification. Collaborating with cross-functional teams to ensure the successful integration and testing of physical designs. The Impact You Will Have: Enhancing the quality and reliability of our digital block implementations. Driving innovation in physical design methodologies and processes. Enabling the successful deployment of high-performance silicon chips. Contributing to the development of cutting-edge technology that powers next-generation applications. Supporting the continuous improvement of our ASIC design flow and tools. Ensuring the seamless integration of physical designs into larger systems and platforms. What Youll Need: In-depth understanding of the ASIC physical design flow steps from gate netlist. Experience in testchip implementation and testing exposure is a plus. Exposure to Synopsys toolset (such as FC/ICC2, Primetime, Formality, ICV) is highly desirable. Experience with FinFET designs is desirable. Experience in working on IO integration with wire-bond or flip-chip design is a big plus. Who You Are: A problem solver with strong analytical skills. Detail-oriented with a focus on quality and reliability. Effective communicator and collaborator. Innovative thinker with a passion for technology. Self-motivated and able to work independently. The Team Youll Be A Part Of: Join a dynamic team of experts focused on pushing the boundaries of physical design and implementation. Our team is dedicated to continuous innovation and excellence, working collaboratively to solve complex challenges and deliver cutting-edge solutions. You&aposll be part of a supportive and inclusive environment where your contributions are valued and your professional growth is nurtured. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

We are seeking a highly skilled Low Power Formal Verification Engineer to join our team. The ideal candidate will possess deep expertise in low power formal verification, advanced constraint development, and a strong understanding of timing analysis in complex SoC designs. This role is critical for ensuring the power efficiency and functional correctness of our designs through rigorous verification methodologies. Roles and Responsibilities: Utilize work experience in Advanced Constraint Verification & post-layout STA (Static Timing Analysis) . Apply expertise in Low Power Formal Verification techniques to ensure power efficiency and functional correctness. Demonstrate expertise in Constraint Development for both Functional and DFT (Design For Testability) aspects. Possess knowledge of IP constraints on interfaces like DDR3/4, Multiprotocol SerDes, ARM core and Subsystem, USB3.0 , which is a significant plus. Apply expertise in MCMM (Multi-Corner Multi-Mode) definitions for comprehensive timing analysis. Possess knowledge in Abstraction definition and creation (e.g., ETM/ILM/Hyperscale ). Understand Extraction & PTSI (Power Timing Static Interconnect) pruning parameter definitions . Define FILL aware timing strategies/flow . Develop DMSA (Design for Manufacturing and System-level Analysis) and ECO (Engineering Change Order) strategy definitions . Conduct Clock Scaling Analysis to ensure robust design operation across different clock frequencies. Required Skills and Qualifications: Expertise in Low Power Formal Verification. Strong background in Constraint Development (Functional, DFT). Proficiency in advanced constraint verification and post-layout STA. Knowledge of IP constraints (DDR3/4, Multi-protocol SerDes, ARM core, USB3.0) is highly beneficial. Expertise in MCMM definitions. Understanding of abstraction definition and creation (ETM/ILM/Hyperscale). Knowledge of extraction & PTSI pruning parameter definitions. Experience with FILL aware timing strategies/flow definition. Familiarity with DMSA and ECO strategy definitions. Ability to perform Clock Scaling Analysis.

As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world-class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Role: Hardware Engineer (Physical Synthesis/Timing) Key Responsibilities & Expertise Should have strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools. Experience with writing timing constraints for synthesis, STA (Static Timing Analysis), timing closure and pipelining at different levels for performance optimization and timing closure. Experience in all aspects of timing closure for multi-clock domain designs . Should be familiar with MCMM (Multi-Corner Multi-Mode) synthesis and optimization . Should have good understanding of low-power design implementation using UPF (Unified Power Format) . Should be able to work independently with design, DFT (Design-for-Test) and PD (Physical Design) team for netlist delivery, timing constraints validation. Should be able to handle ECOs (Engineering Change Orders) and formal verification and maintain high quality matrix. Required Skills Experience with scripting language such as Perl/Python, TCL . Experience with different power optimization flows or techniques such as clock gating . Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.