Synthesis + STA Engineer (SI80FF RM 3488) Sourceright Technologies

8.0 - 13.0 years

6 - 8 Lacs

bengaluru, karnataka, india

On-site

Strong understanding of timing closure for multi-clock, high-frequency timing, congestion, crosstalk, and area-sensitive designs. Collaborate with RTL designers for constraint development and cleanup. Proficient in Synopsys/Cadence tools with hands-on experience in advance features of Design compiler and PrimeTime SI. Deep expertise in low-power design (UPF/CPF), clock gating, logic optimization, and integration of high-speed interfaces like DDR and PCIe Provide technical leadership to successful tape outs at advanced technology nodes (7nm, 5nm and 3nm). Good scripting, communication and debugging skills.

Posted 2 months ago

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FPGA Engineer Talent Corner Hr Services

1.0 - 3.0 years

3 - 4 Lacs

Bengaluru

Hybrid

We are hiring an FPGA Engineer with experience in RTL design, timing closure, and logic optimization on Xilinx/Intel FPGAs to work on digital signal processing solutions in a collaborative, multidisciplinary engineering environment.

Posted 4 months ago

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