Lead engineer VLSI

As a Verification Engineer, you will be responsible for developing and implementing comprehensive verification plans using industry-standard methodologies such as UVM. Your role will involve designing and writing robust verification environments (testbenches) to achieve high code coverage. Utilizing simulation tools like ModelSim, Cadence Incisive, and Synopsys VCS will be essential for verifying RTL functionality. You will play a crucial part in debugging and analyzing verification failures to identify the root cause of design issues. Collaboration with RTL design engineers to resolve functional bugs and ensure design revisions meet verification requirements will be a key aspect of your responsibilities. Additionally, your involvement in code reviews and ensuring adherence to verification coding standards will be significant. Staying up-to-date with the latest verification tools and methodologies will be crucial for your continuous growth and success in this role. Qualifications required for this position include a Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (a Master's degree is a plus). You should have 5-7 years of experience in design verification for ASICs or SoCs. A strong understanding of digital design principles, including combinational logic and sequential logic, is essential. Your proven ability to develop and debug complex verification environments, proficiency in Verilog or VHDL, and experience with verification methodologies like UVM will be highly valued. Experience with simulation tools and scripting languages such as Python and Perl would be advantageous. Excellent analytical and problem-solving skills, along with strong communication and collaboration abilities to work effectively in a team environment, are qualities that will contribute to your success in this role.,