IO Layout Staff Engineer

10 - 15 years

3 - 7 Lacs

Posted:1 day ago| Platform: Naukri logo

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Job Type

Full Time

Job Description

  • Take full ownership of End-to-End IP development and support for IO IPs Define specifications, define topologies, design/verify, guide layout team, post silicon validation, customer support on IP bugs
  • Mentor junior engineers in block level designs
  • Create required testbenches and perform DC, AC, Transient, STB, EMIR simulations
  • Create design documents and drive Design reviews
  • Be a creative problem solver, and look for innovation in design
  • Work with cross-geo, cross-vertical teams to understand requirements and communicate resolution
Other Responsibilities:
  • Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs
Required Qualifications :
  • BS + 10 years/ MS + 8 years/ PhD + 6 or more years of experience working on IO Design - GPIO, LVDS, SSTL, HSTL, MIPI
  • Deep understanding of Standard CMOS, FinFet and SOI technologies
  • Multiple successful tapeouts in IO IPs
  • Experience with silicon debug is a big plus
  • Expert knowledge of Cadence tools Virtuoso schematic editor, ADE-XL, Spectre
  • Supervise layout engineers in delivering high quality layouts
  • Must have good technical verbal and written communication skills and ability to work with cross functional teams is necessary
  • Be able to collaborate with program and technical design leads on multiple concurrent projects.
  • Should have excellent problem-solving skills, written & oral communication, teaming & interpersonal skills
  • Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs
  • Language Fluency Fluent in English Language written & verbal

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