Job Description : 7+ years of experience in design verification with at least 2+ years in a leadership role. Expertise in SystemVerilog, UVM, assertions (SVA), and scripting languages (Python, Perl, Tcl, etc.). Solid understanding of digital design, SoC architecture, and bus protocols. Experience with simulation and debug tools (VCS, ModelSim, Questa, Verdi, DVE, etc.). Strong analytical and problem-solving skills with a keen attention to detail. Excellent communication, project management, and interpersonal skills. Good Working experience on protocol like , AXI, PCIe, CXL, Ethernet, DMAC, USB, UFS·
Company Description Founded in 2013, InSemi Technology Services Pvt. Ltd. specializes in VLSI design services, embedded systems product development, and bridging academia with industry. Our expertise spans across Foundation IP, ASIC design/verification, and technology infrastructure including CAD and PDK development. Our embedded systems team excels in IoT, PCB design, product analysis, and embedded software development. We foster an environment of technical excellence and innovation, supported by a dynamic management team. Role Description This is a full-time on-site role for a Senior STA Engineer based in Chennai. The Senior STA Engineer will be responsible for performing Static Timing Analysis (STA) on complex integrated circuits, developing timing constraints, and collaborating with design and verification teams. Additional tasks include timing closure, analyzing and resolving timing violations, and documenting timing reports. Qualifications Proficiency in Static Timing Analysis (STA) and timing closure techniques Experience with developing and managing timing constraints Familiarity with timing tools such as PrimeTime or Tempus Strong understanding of VLSI design flow and methodologies Excellent problem-solving skills and attention to detail Effective communication and teamwork abilities Master's or Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
You will be joining Insemi Technologies as a Staff or Lead Verification Engineer in Bengaluru. Your primary responsibility will be to own the functional verification of RTL designs for PCIe / UCIe protocols. This will involve building and enhancing UVM testbench components such as scoreboard, driver, and monitor. You will also be debugging complex design/verification issues and collaborating with teams to ensure architecture compliance. Additionally, you will play a key role in improving verification methodology and processes. To excel in this role, you should have at least 5-10 years of verification experience with a strong knowledge of PCIe and/or UCIe protocols. Expertise in SystemVerilog & UVM is essential, along with solid debugging and analytical skills. A degree in B.E/B.Tech or M.E/M.Tech in EE/CE or related fields is required, and any experience in VLSI design services would be a bonus. If you are passionate about PCIe / UCIe protocol verification and possess the necessary skills and experience, we encourage you to send your resume to Jennifer Margaret at jennifer.margaret@insemitech.com. Join us at Insemi Technologies and let's build something exceptional together.,
Good Knowledge on Synthesis Good working knowledge on Pre and Post layout STA Should have handled a team of 8-10 engineers Timing Budgeting knowledge Knowledge on power and voltage domain. Good in Scripting . Good knowledge on constraints.