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8.0 - 13.0 years
3 - 5 Lacs
hyderabad, telangana, india
On-site
Responsibilities Manage hierarchical scan insertion and ATPG flow Integrate and verify MBIST at the RTL level Handle RTL integration, verification, gate-level coverage, and GLS enablement for LBIST Implement and verify IEEE1149.1 JTAG and IJTAG standards Lead post-silicon debug activities related to DFT patterns Collaborate daily with RTL design, physical design, and verification teams Mentor and guide junior engineers in DFT methodologies
Posted 2 months ago
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