3 Ieee 1500 Jobs

DESCRIPTION The team that built the innovative Silicon IP AZ1 Neural Edge that is powering the latest generation of Echo devices is looking for a Senior DFT Engineer to continue to innovate on behalf of our customers. We are a part of Amazon Lab126 that revolutionized reading with our Kindle family of products and re-imagined user experience through Echo and Alexa. We want you to help us build on the success of our first generation of ML accelerator at edge. Work hard. Have fun. Make history. We are seeking a seasoned and strategic Sr DFT Engineer to Lead end-to-end Design-for-Test (DFT) planning, execution, and silicon readiness for complex SoCs. This role demands deep technical expertise, hands-on ownership, and proven leadership in taking chips from design to volume production. As a Senior DFT Engineer, you will be both the technical owner and hands-on driver of the DFT strategy and execution across complex, high-performance SoCs. This role requires deep technical expertise, the ability to architect scalable and robust DFT solutions, and the discipline to personally engage in implementation and debug. You will work alongside world-class design, validation, and test teams to ensure first-pass silicon success and scalable production test readiness. Ideal for a seasoned leader, this role combines strategic ownership with direct execution, driving full lifecycle accountability - from early DFT architecture planning to high-volume silicon bring-up and yield ramp. Key job responsibilities Key job responsibilities ? Lead development & implementation of DFT architecture including system level DFT for a full chip ? Write and guide others in writing design flow and project documentation. ? Own DFT planning, milestone tracking, and cross-functional checklist reviews. ? Oversee design, insertion, and verification of DFT logic and components into full SoC and subsystem RTL netlists. ? Review and sign-off SoC level DFT mode timing closure using static timing analysis ? Drive the sign-off on a generation of high-quality test and debug patterns for high coverage on silicon ? Keep informed on and introduce new technology into Design-for-Test process as appropriate. BASIC QUALIFICATIONS Education: BS/BE or MS/ME in Electrical Engineering, Computer Engineering, or related field. Experience: ? 15+ years in SoC/ASIC DFT, including 3+ years Leading DFT. ? Proven DFT experience leading multiple SoCs/ASICs (end-to-end) from architecture to high-volume production. DFT Architecture Expertise: Proven capability in architecting and implementing DFT strategies at both subsystem and top-level, including: ? Scan architecture, compression, and ATPG implementation for high fault coverage and test quality. ? MBIST, BISR, and BIHR flows, including advanced shared-bus memory BIST integration. ? IEEE 1149.x (Boundary Scan), IEEE 1500, and IEEE 1687 (IJTAG) test architectures. ? DFT-Aware STA closure, including constraint generation and timing convergence strategies for shift and capture paths. ? RTL and gate-level debug, including mismatch triage and simulation correlation. ? Insertion and Validation of EFUSE & OTP controllers and related structures during DFT implementation. Tool Proficiency: Deep hands-on experience with Tessent / Industry Std EDA tools, including: ? IJTAG ICL extraction and PDL modeling. ? DFT logic insertion, pattern generation, and diagnostics. Design Background: ? Experience in writing verilog/system verilog RTL related to DFT logic design. ATE Test Readiness: Lead DFT-to-ATE handoff, including: ? Drive generation and sign-off of high-quality test and debug patterns to meet DFT coverage targets. ? Pattern validation, format conversion, and debugging across wafer sort and final test. ? Collaboration with PE/Test teams for silicon correlation and production test optimization, yield improvements. Silicon Debug: ? Drive post-silicon validation, failure triage, and yield learning using SCAN diagnosis and MBIST repair signature analysis. Automation Skills: ? Ability to build and maintain scalable DFT automation flows using Python, Tcl, or Perl. Collaboration: ? Proven success driving cross-functional teams involving RTL, physical design, validation, PE, and manufacturing. Execution Excellence: ? Known for being proactive, detail-oriented, and independently accountable for tapeout and post-silicon success. PREFERRED QUALIFICATIONS Leadership: ? Led multi-site/global DFT teams, mentoring engineers and managing design reviews. ? Drove design-for-test planning in collaboration with customers or design services partners. Technical Depth: ? Strong understanding of DFT-Aware yield improvement and FA, including DPPM reduction strategies. ? Ability to correlate pre-silicon vs ATE pattern behavior and debug marginality/escape issues. ? Exposure to Design-for-Debug (DfD) features like trace buffers, signature capture, and observability enhancement. Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit for more information. If the country/region you're applying in isn't listed, please contact your Recruiting Partner.

Job Description : We are looking for a VLSI MBIST Engineer with strong expertise in Memory Built-In Self-Test (MBIST) methodologies for ASIC/SoC designs. The ideal candidate should have hands-on experience using Synopsys SMS tool and a solid understanding of MBIST test development, pattern generation, and fault simulation. Key Responsibilities : Develop and implement MBIST algorithms and test patterns for embedded memories (SRAM, DRAM, ROM, CAM) Use Synopsys SMS tool for MBIST pattern generation and validation Perform fault modeling, fault simulation, and fault coverage analysis Integrate MBIST macros into SoC designs in collaboration with RTL and physical design teams Debug MBIST issues in pre- and post-silicon stages Document MBIST flows, generate test reports, and provide support for DFT reviews Stay updated on industry trends and best practices in MBIST and memory testing Required Skills : B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, VLSI, or related fields 4+ years of experience in MBIST implementation and validation Strong experience with Synopsys SMS tool Proficiency in scripting languages like TCL, Perl, or Python Good knowledge of Verilog/SystemVerilog and digital design fundamentals Familiarity with simulation tools like VCS, ModelSim Preferred Skills : Experience with DFT tools such as Tessent Knowledge of ATPG, JTAG (IEEE 1149.1), and IEEE 1500 standards Exposure to silicon bring-up and failure analysis

Introduction As a Hardware Developer at IBM, youll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable IBM customers to make better decisions quicker on the most trusted hardware platform in todays market. Your Role and Responsibilities : We are seeking highly motivated DFT engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, and delivery of DFT patterns for IBMs microprocessor chip design team. As a member of functional DFT team ( Power on Reset, Architecture Verification Program, Array BIST teams ), you will be required but not restricted to pattern generation, simulation, validation, characterization, delivery to TAE, IBMs Hardware Bring-up and Silicon Debug Your role and responsibilities We are seeking highly motivated DFT engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, and delivery of DFT patterns for IBMs microprocessor chip design team. As a member of functional DFT team ( Power on Reset, Architecture Verification Program, Array BIST teams ), you will be required but not restricted to pattern generation, simulation, validation, characterization, delivery to TAE, IBMs Hardware Bring-up and Silicon Debug Required education Bachelors Degree Preferred education Masters Degree Required technical and professional expertise 5-9 years experience in DFT on complex designs involving scan insertion, compression, MBIST, ATPG, simulations and IP integration and validation.Proven expertise in analysing and resolving DRCs/TSVs .Hands-on experience in pattern generation for various fault models, pattern retargeting and debugging techniques to address low coverage issues.Hands-on experience with Gate-Level DFT verification, both with and without timing annotations.Well versed with industry standard test techniques and advanced DFT features like SSN, IJTAG, IEEE 1500, Boundary scan , LBIST and STA constraint delivery .Hands on experience on industry standard tools used for DFT featuresProficiency in scripting languages such as TCL, Perl or Python to automate design and testing tasks.Worked with cross functional teams like design, STA & tester teams for ensuring top quality of DFT deliverables and DFT support and hand offs.Excellent analytical and problem-solving skills, with a keen attention to detail.Strong communication and collaboration skills, with the ability to work effectively within cross-functional teams Fundamentals in micro controller architecture, embedded firmware, functional verification and RTL design . Experience working with ATE engineers for silicon bring up, silicon debug and validation. . Experience in processor flow and post silicon validation Preferred technical and professional experience Hiring manager and Recruiter should collaborate to create the relevant verbiage.