IC Connections

This is a full-time on-site role for a Standard Cell & Memory Characterization Engineer located in Hyderabad. The Engineer will be responsible for the day-to-day tasks of developing standard cells and memory characterization methodologies, performing detailed analysis and verification, conducting research, and working with wireless technologies. The role requires a collaborative approach to problem-solving and a commitment to quality and precision in delivering engineering solutions. STD Cell Characterization (PrimeLib, Silicon Smart) Able to characterize basic standard cells. Static & Timig Analysis of SRAM and DRAM. Writing constraints and analysing the STA report. Reporting violations to design team. STA at block/top/cell level .lib QA, ARC files, timing constraints DRAM circuit/block-level analysis Parasitic extraction, tape-out support EDA Tools: Synopsys, Cadence, TCL, Python