7 Hierarchical Designs Jobs

As an ASIC Physical Verification Engineer at Micron Technology, you will play a crucial role in achieving the best Power, Performance, and Area (PPA) by ensuring the closure of Block/Chip Tile PV. Your responsibilities will involve DRC & LVS closure for both Block and Full Chip designs in complex hierarchical structures at 5nm/3nm nodes. You will have the opportunity to collaborate with various teams such as IR, IP, ESD, and PD to ensure Physical Verification Convergence and resolve conflicts effectively. Additionally, you will be expected to handle multiple blocks simultaneously with minimal supervision, ensuring Full Chip LVS & DRC closure and Analog integration closure for all IPs used in...

As a Physical Design Engineer with Innovus skills, your role will involve the following key responsibilities: - Solid experience in place & route flow, including placement guidelines, clock-tree synthesis, routing, and timing optimizations. - Experience with hierarchical designs and/or Low Power implementation is considered an advantage. - Proficiency in Synthesis, interfacing with RTL, and implementation. - Expertise in Floorplan design, which includes placement of hard macros and congestion reduction techniques. - Familiarity with Static Timing Analysis activities, parasitic extractions, and sign-off requirements. - Knowledge of Physical Verification processes such as DRC/LVS/DFM and chip ...

Hi All, Eximietas Hiring Senior Physical Design Leads/Managers. Experience: 10+ Years. Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA. Anyone with a Valid H1B or Already in US. About the job Qualification Required: Typically requires a minimum of 10+ years of experience in Physical Design with mainstream P&R tools Bachelors OR Masters Degree Engineering in Electronics or Electrical or Telecom or VLSI Engineering. Roles And Responsibilities Working on 10nm/7nm/5nm or lower nodes designs with various customers for deployment. Expertise in solving customers problems for critical designs to achieve desired performance, area, and power targets. Responsible for developin...

You have solid experience in place & route flow, including placement guidelines, clock-tree synthesis, routing, and timing optimizations. Additionally, you have experience in hierarchical designs and/or Low Power implementation. Your expertise also extends to synthesis, interfacing with RTL, and implementation. You are skilled in floorplan design, which includes the placement of hard macros and congestion reduction techniques. Furthermore, you have experience in Static Timing Analysis activities, parasitic extractions, and sign-off requirements. Knowledge of Physical Verification (DRC/LVS/DFM, chip finishing) is considered an added advantage. Qualifications Required: - 5+ years of experience...

Role Overview: As a part of Micron Technology, you will play a crucial role in innovating memory and storage solutions, accelerating the transformation of information into intelligence. Your expertise in ASIC Physical Verification and overall design flow will be instrumental in achieving the best PPA for block/chip PV closure and ensuring DRC & LVS closure for complex hierarchical designs. Key Responsibilities: - Achieve block/chip PV closure to optimize PPA - Conduct DRC & LVS closure for block and full chip designs in 5nm/3nm nodes - Collaborate with IR, IP, ESD, and PD teams to ensure Physical Verification convergence - Work on multiple blocks simultaneously with minimal supervision - Ens...

You will be part of ACE India, in the P-Core design team driving Intel's latest CPUs in the latest process technology. As a member of the team, you will lead the design analysis and methodologies of various memory blocks, ensuring they meet over 5GHz frequency and low-power digital designs with optimal area utilization. Your role will involve a deep understanding of different memory design concepts such as SRAM, RF, and ROM along with expertise in static timing analysis concepts. Close collaboration with Layout and Floor planning teams will be essential for successful back end design implementation of new features. Additionally, you will specialize in memory post-silicon analysis and possess...

Experience place & route flow, hierarchical design,Synthesis, Static Timing Analysis ,7nm, hierarchical designs