Posted:1 month ago|
Platform:
On-site
Full Time
Digital RTL ASIC Design Engineer (VLSI):
Exp: 7 to 15 years
Mandatory skills:
SOC Development
RTL Coding & IP Design, Micro Architecture
UART/SPI/I2C
DDR/Ethernet/PCIe
Lint/CDC/Verdi/Xcellium
Python, Makeflow, Shell
Job Type: Full-time
Pay: ₹1,500,000.00 - ₹4,500,000.00 per year
Schedule:
Work Location: In person
USP Software Solutions Pvt Ltd
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