Design Verification Lead

As a Design Verification Lead, you will play a crucial role in leading verification engineers to guarantee the delivery of high-quality product releases within the specified timelines. Your responsibilities will involve collaborating effectively with cross-functional teams such as design engineering and hardware development. In addition, you will be responsible for developing testbenches utilizing SystemVerilog/UVM OOP principles. Your expertise will be crucial in suggesting optimization techniques for complex HDL code. **Key Responsibilities:** - Lead verification engineers to ensure high-quality product releases within specified timelines. - Collaborate effectively with cross-functional teams like design engineering and hardware development. - Develop testbenches using SystemVerilog/UVM OOP principles. - Suggest optimization techniques for complex HDL code. **Qualifications Required:** - Bachelor's degree in Electrical Engineering, Computer Engineering, or related field. - Proven experience in leading verification teams and delivering high-quality product releases. - Proficiency in SystemVerilog/UVM and OOP principles. If you have any additional details about the company in the job description, please provide them for a more comprehensive job description. As a Design Verification Lead, you will play a crucial role in leading verification engineers to guarantee the delivery of high-quality product releases within the specified timelines. Your responsibilities will involve collaborating effectively with cross-functional teams such as design engineering and hardware development. In addition, you will be responsible for developing testbenches utilizing SystemVerilog/UVM OOP principles. Your expertise will be crucial in suggesting optimization techniques for complex HDL code. **Key Responsibilities:** - Lead verification engineers to ensure high-quality product releases within specified timelines. - Collaborate effectively with cross-functional teams like design engineering and hardware development. - Develop testbenches using SystemVerilog/UVM OOP principles. - Suggest optimization techniques for complex HDL code. **Qualifications Required:** - Bachelor's degree in Electrical Engineering, Computer Engineering, or related field. - Proven experience in leading verification teams and delivering high-quality product releases. - Proficiency in SystemVerilog/UVM and OOP principles. If you have any additional details about the company in the job description, please provide them for a more comprehensive job description.