ASIC Design Verification Lead, Silicon Google

10.0 - 14.0 years

0 Lacs

karnataka

On-site

The ideal candidate for this role should have a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. Additionally, a minimum of 10 years of experience in creating and utilizing verification components and environments in standard verification methodology is required. Experience in verifying digital systems using standard IP components/interconnects such as microprocessor cores and hierarchical memory subsystems is also essential. Preferred qualifications include a Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with a focus on computer architecture. Candidates should also have experience in low-power design verification, as well as familiarity with Interconnect Protocols like AHB, AXI, ACE, CHI, CCIX, and CXL. Furthermore, expertise in Architectural backgrounds related to Caches Hierarchies, Coherency, Memory Consistency Models, DDR/LPDDR, PCIe, Packet Processors, Security, Clock, and Power Controllers is advantageous. As a member of the team, you will be involved in developing custom silicon solutions that drive Google's direct-to-consumer products. Your contributions will play a crucial role in shaping innovative products that are cherished by millions globally. Your skills and knowledge will influence the future of hardware experiences, ensuring exceptional performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. By combining Google AI, Software, and Hardware expertise, our team creates groundbreaking experiences that are incredibly beneficial. We are dedicated to researching, designing, and developing new technologies and hardware to enhance computing speed, seamlessness, and power. Our ultimate goal is to enhance people's lives through innovative technology solutions. Key Responsibilities: - Verify designs using advanced verification techniques and methodologies. - Collaborate across functions to troubleshoot failures and validate the functional accuracy of designs. - Develop comprehensive test plans encompassing verification strategy, environment, components, stimulus, checks, and coverage, ensuring user-friendly documentation. - Lead the verification of next-generation configurable Infrastructure IPs, interconnects, and memory subsystems. - Collaborate with design engineers to debug tests and deliver functionally sound blocks and subsystems. Monitor coverage metrics to pinpoint verification gaps and demonstrate progress towards tape-out.,

Posted 3 weeks ago

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ASIC Design Verification Associate Engineer Google

3.0 - 7.0 years

0 Lacs

karnataka

On-site

As a Verification Engineer at Google, you will play a crucial role in ensuring the functionality and performance of Google's custom silicon solutions. You will be responsible for verifying digital systems, including infrastructure IP, interconnects, caches, memory management, and system services. Your expertise will be instrumental in shaping the next generation of hardware experiences, delivering unmatched performance, efficiency, and integration. Your responsibilities will include planning and executing the verification of configurable Infrastructure IPs, interconnects, and memory subsystems. You will develop and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM). Additionally, you will create cross-language tools and scalable verification methodologies to ensure comprehensive testing coverage. To excel in this role, you should have a Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience. You should possess experience in verifying digital systems using standard IP components/interconnects, such as microprocessor cores and hierarchical memory subsystems. Proficiency in Design Verification Test, SystemVerilog, Verilog, Computer Architecture, System On a Chip, C, C++, and Python is required. Experience in creating and using verification components and environments in standard verification methodology, scripting languages, and software development frameworks is essential. Preferred qualifications for this position include a Master's degree or PhD in Electrical Engineering or Computer Science, along with 3 years of experience in areas such as Caches Hierarchies, Coherency, Memory Consistency Models, DDR/LPDDR, PCIe, Packet Processors, Security, or Clock and Power Controllers. Experience with building verification methodologies spanning simulation, emulation, and Field Programmable Gate Array (FPGA) prototypes is advantageous. Knowledge of Interconnect Protocols (e.g., AHB, AXI, ACE, CHI, CCIX, CXL), performance verification of SOCs, pre-Silicon analysis, and post-Silicon correlation is also beneficial. Join our team at Google and be part of the innovation that drives the future of direct-to-consumer products. Your contributions will have a global impact, shaping products loved by millions worldwide. Embrace the opportunity to work on the verification of Google's System on a Chip (SOC) offerings, collaborating with hardware architects and design engineers to deliver cutting-edge hardware experiences. Your role will involve developing performance Virtual IP address (VIPs) for supported protocols, deploying verification stacks across diverse IPs, and building generalized system topology abstractions. Together, we will develop methodologies and tools to tackle complex challenges and advance technology for the betterment of society.,

Posted 1 month ago

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