Job
Description
Minimum qualifications: Bachelors degree in Electrical or Computer Engineering or equivalent practical experience 6 years of experience with ARM-based System on a chip (SoCs), interconnects and Application-Specific Integrated Circuit (ASIC) methodology 5 years of experience with Register-Transfer Level (RTL) design using Verilog/System Verilog and microarchitecture Experience with a coding language like Python or Perl Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Science, or equivalent practical experience 6 years of industry experience with Internet Protocol (IP) design Experience with methodologies for Register-Transfer Level (RTL) quality checks (e g , Lint, CDC, RDC) Experience with methodologies for low power estimation, timing closure, synthesis About The Job Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products You'll contribute to the innovation behind products loved by millions worldwide Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration In this role, you will design foundation and chassis Internet Protocols (IPs) (e g , Network on Chip (NoC), Clock, Debug, IPC, Memory Management Unit (MMU) and other peripherals) for Pixel System on a chip (SoCs) You will collaborate with members of architecture, software, verification, power, timing, synthesis etc to specify and deliver a quality Register-Transfer Level (RTL) You will solve technical problems with micro-architecture, low power design methodology and evaluate design options with performance, power and area in mind Google's mission is to organize the world's information and make it universally accessible and useful Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful We aim to make people's lives better through technology Responsibilities Participate in test planning and coverage analysis Develop Register-Transfer Level (RTL) implementations that meet power, performance and area goals Participate in synthesis, timing/power closure and Field Programmable Gate Array (FPGA) and silicon bring-up Perform Verilog/SystemVerilog RTL coding, functional, performance simulation debug and Lint/CDC/FV/UPF checks Create tools/scripts to automate tasks and track progress Google is proud to be an equal opportunity workplace and is an affirmative action employer We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status We also consider qualified applicants regardless of criminal histories, consistent with legal requirements See also Google's EEO Policy and EEO is the Law If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form
