Sr Principal Design Engineer Cadence Design Systems

11.0 - 12.0 years

8 - 15 Lacs

Noida, Uttar Pradesh, India

On-site

Define the DFT Architecture for the next generation SoCs. Implementation & verification including Scan, PMBIST, JTAG and other DFT s related logic. Define and develop methodology for DFT insertion, pattern development, manufacturing tests, verifications, etc Working closely with cross functional teams to develop and verify DFT s structures and constraints. Perform RTL and gate level (no-timing and timing) simulations to verify DFT functionality. Work closely with Test Engineering for test program development and Silicon bring up, diagnosis, Yield improvement, etc. Work closely with EDA RnD teams to propose and implement new features. Requirements : B. Tech /BE/ME/M Tech with8-15+ years of re...

Posted 3 months ago

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