Senior RTL Design Engineer

We are seeking experienced SoC Verification and Emulation Engineers to support server platform verification activities. The candidate will be responsible for developing and executing verification plans, debugging complex SoC issues, and driving verification closure in pre-silicon and emulation environments.

The role requires strong expertise in SystemVerilog/UVM-based verification methodologies, Python-based automation, and functional validation of critical infrastructure features including Security, Reset, RAS, Clocking, Power Management, GPIO, Debug and Fuse flows.

• Strong expertise in SoC Pre-Silicon Verification and Emulation using SystemVerilog, UVM, Assertions (SVA), Functional Coverage, and Testbench Development.
• Hands-on experience in developing verification environments, checkers, scoreboards, test cases, and regression execution frameworks.
• Proven experience in verifying Debug Fabrics, including VISA, Trace, Observability, Trigger, and TAP/JTAG-based validation.
• Experience in validating SoC Platform Infrastructure and System Control Flows, including Reset, Security, RAS, Fuse, GPIO, Clocking, and Power Management.
• Strong proficiency in Python scripting and automation for pre-silicon and emulation-based test execution.
• Hands-on experience with SoC emulation platforms, including test execution, debug, regression management, and coverage closure.
• Expertise in verification debug tools, waveform analysis, failure triage, and root-cause analysis of complex SoC issues.
• Ability to analyze and resolve SoC integration and functional validation issues in collaboration with architecture, design, and firmware teams.
• Good understanding of Intel Xeon/Client verification methodologies and validation flows.

Strong analytical, communication, and problem-solving skills with the ability to work effectively in cross-functional global teams.

• Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, Computer Science, or a related field.