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Senior Memory Design Lead Engineer

8 - 12 years

0 Lacs

karnataka

Posted:17 hours ago| Platform: Shine logo

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Skills Required

understanding of computer architecture concepts basic understanding of cmos transistors their behaviors understanding of high speedlow power cmos circuit design clocking scheme static complex logic circuits understanding of power versus performance versus area tradeoffs in typical cmos design engineering demeanor passion for circuit design good interpersonal skills basic scripting languages eg perltclpython experience of working on cadence synopsys flows experience with circuit simulation optimization of standard cells

Work Mode

On-site

Job Type

Full Time

Job Description

As a Senior Memory Design Lead Engineer, you will be responsible for developing memory compilers and memory Fast Cache instances for the next generation Cores in order to achieve outstanding PPA. Key Responsibilities: - Understanding of computer architecture and concepts. - Basic understanding of CMOS Transistors and their behaviors. - Understanding of high speed/low power CMOS circuit design, clocking scheme, Static and complex logic circuits. - Understanding of Power versus Performance versus Area trade-offs in typical CMOS design. - Having an engineering demeanor and Passion for Circuit design. - Good interpersonal skills are expected. - Minimum 8+ Yrs of experience in SRAM / memory design Margin, Char and its related quality checks. Qualifications Required: - Minimum 8 years of experience in SRAM / memory design Margin, Char and its related quality checks. - Understanding of computer architecture and concepts. - Basic understanding of CMOS Transistors and their behaviors. - Understanding of high speed/low power CMOS circuit design, clocking scheme, Static and complex logic circuits. - Understanding of Power versus Performance versus Area trade-offs in typical CMOS design. If you are interested in this position, you can apply or share your profile at Krishnaprasath.s@acldigital.com.,

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