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3.0 - 6.0 years
6 - 10 Lacs
bengaluru
Work from Office
Design Verification and RTL/GLS debug Regression Run , Assertion and Coverage Closure activities Need to be good in SV/UVM Roles and Responsibility Develop and implement verification environments using System Verilog and UVM. Verify IP, SOC, and pre-silicon designs. Collaborate with cross-functional teams to identify and resolve design issues. Create and maintain testbenches and testcases for verifying complex digital circuits. Analyze and debug verification results to ensure design quality. Participate in the development of new verification methodologies and techniques. Experience (years) : 3+ years Education Qualification: BE/ME.
Posted 9 hours ago
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