2.0 - 4.0 years

0 Lacs

Noida, Uttar Pradesh, India

On-site

Sr. Engineer - ASIC Digital Design (Physical Implementation/Design/STA, 2+ years of exp) We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly skilled and experienced ASIC Digital Design Engineer passionate about working on the latest processes for STA and physical implementation flows on cutting-edge technology nodes. You thrive in dynamic environments and excel in collaborating with functional teams to optimize and develop IO validation vehicles, Mixed Signal IPs, 3DIO PHYs and UCIe-3D PHY. You have a strong focus on Timing Closure and are adept at defining signoff criteria. Your background includes extensive experience with ASIC design flow, hierarchical physical design strategies, and a deep understanding of sub-micron technology issues. You possess a strong knowledge of timing analysis, constraints management, and various verification strategies, including Primepower-based power analysis. Your scripting skills are excellent, and you are innovative, self-motivated, and able to work both independently and as part of a team. Your communication skills, both verbal and written, are outstanding, and you have a desire to understand RTL/Timing signoff criteria. What Youll Be Doing: Working on new processes for physical implementation flows and cutting-edge technology nodes. Collaborating with functional teams to optimize and develop Qualificaition vehicles and 3D PHYs. Defining signoff criteria with a strong focus on Timing Closure. Maturing the physical implementation guide used for customers and internal hardening teams. Participating in next-generation physical design methodology and flow development. Performing physical design implementation, including synthesis, floor planning, PG Grid design, PnR, CTS, STA, and power/signal integrity signoff. Evaluating PPA targets (Area/Speed/Power) and collaborating with the design team to improve design and constraints. The Impact You Will Have: Ensuring the optimization and successful implementation of cutting-edge technology nodes. Contributing to the development of high-performance silicon chips and software content. Enhancing the efficiency and performance of Synopsys IPs through rigorous timing closure and signoff criteria. Improving customer satisfaction by maturing physical implementation guides. Supporting the achievement of Synopsys' operational goals through innovative design solutions. What Youll Need: Extensive experience with ASIC design flow and hierarchical physical design strategies. Strong background in timing analysis, constraints management, and frontend synthesis. Experience with physical-aware synthesis, formality, and various verification strategies. Knowledge of Primepower-based power analysis and clock gating for power reduction. Fair knowledge of FC design planning methodologies, floor planning, and PG Grid creation using Synopsys Tools. Strong physical implementation flow debugging skills and scripting abilities. Who You Are: Innovative, self-motivated, and able to work independently or as a team player. Excellent verbal and written communication skills. Strong analytical and problem-solving abilities. Passionate about continuous learning and staying updated with the latest technological advancements in ASIC digital design. The Team Youll Be A Part Of: You will join a highly skilled and collaborative team focused on developing and optimizing physical design flows for cutting-edge technology nodes. The team is dedicated to innovation, continuous improvement, and delivering high-performance solutions that meet the evolving needs of our customers. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

Posted 1 month ago

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Architect - ASIC Verification Synopsys

20.0 - 22.0 years

3 - 10 Lacs

Noida, Uttar Pradesh, India

On-site

Responsible for PCIe/CXL next-gen Controller IP features Customer pre/post sales PCIe/CXL protocol related communication Utilizing advanced design methodologies and tools to achieve high-quality results Mentoring and guiding other engineers, promoting best practices, and fostering a culture of continuous improvement Communicating with internal and external stakeholders to align on project goals and deliverables. What You ll Need: Extensive experience in digital ASIC design and physical aware synthesis. In-depth knowledge of PCIe, CXL , AXI, CHI and similar IO protocols. Proficiency in advanced digital design tools and methodologies. Strong problem-solving skills and the ability to work independently. Excellent communication skills for effective collaboration with diverse teams. Experience of 20+ years in relevant domain. Who You Are: A mentor who fosters talent and encourages innovation. A proactive problem solver who thrives in complex environments. An effective communicator with the ability to convey technical concepts to a broad audience. A team player who values collaboration and diversity.

Posted 3 months ago

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