MTS Silicon Design Engineer

MTS Silicon Design Engineer

As a SubSystem Integration Engineer on the AMD Infinity Fabric team, you will be working with SOC team for integrating our subsystem into System on Chip (SoC) designs.

You will be the key point of contact for debugging and resolving any issues that arise at the SoC level, ensuring seamless functionality throughout the project lifecycle.

You will also collaborate with various teams to drive milestone execution, track features, and maintain robust documentation, helping to bring system-level insights to integration.

Key Responsibilities:

• Assist in integration of Data Fabricsubsystem into SoC designs, debug issues, and serve as the primary contact for any subsystem-related concerns.
• Understand the scope, track features, and ensure key functionalities align with project milestones.
• Manage checklists and ensure successful delivery of each phase, meeting performance and quality metrics.
• Maintain and update tools and components throughout development stages.
• Oversee the release process, ensuring accurate documentation of features, exceptions, and necessary compliance clearances.
• Provide support for emulation and testing, addressing integration challenges as needed.

Qualifications:

• Bachelor's or Master's in Electrical or Computer Engineering, or related field.
• Prior experience in integrating IPs/Subsystems into SoCs is a big plus.

Skills:

• Proficiency in System Verilog, UVM and general DV methodology.
• Proficiency in scripting (Python, Perl, etc.).
• Strong debugging and problem-solving abilities.
• Ability to drive issue resolution and facilitate team collaboration.
• Effective communication and email etiquette.

Desired Qualities:

• Strong leadership in coordinating across teams and pulling in resources to resolve complex technical issues quickly.
• Ability to adapt to a dynamic environment, prioritize tasks, and work under pressure to meet critical milestones.
• A mindset focused on continuous learning, understanding the bigger picture of Subsystem design and how it integrates into SoC.