HW Design_DFT

The ideal candidate for this role should possess a strong understanding of Design for Testability (DFT) concepts and have hands-on experience in DFT implementation and Extraction. You should have expertise in ATPG (Automatic Test Pattern Generation) and DRC (Design Rule Check) analysis. Proficiency in Coverage Analysis for SAF/TDF is essential for this position. Additionally, you should be adept at conducting simulations with and without timing, along with independent debugging capabilities. Experience in post-silicon support and debugging on ATE (Automated Test Equipment) is highly desirable. A positive attitude and the ability to work effectively as part of a team are important qualities we are looking for in a candidate. The acceptable education titles/degrees for this role include BE, BTECH, ME, and MTECH. Key Skills: DFT, Scan, ATPG, post-silicon If you are someone with a solid foundation in DFT and practical experience in Scan and complex DRCs involving multiple power domains, this opportunity is for you. You should be skilled in ATPG activities such as Stuck-at and TDF, including advanced techniques. Proficiency in debugging issues related to ATPG and Coverage analysis, as well as simulations with and without timing, will be crucial for success in this role. Moreover, prior experience in post-silicon debug activities will be an advantage. A proactive approach to problem-solving and a collaborative mindset are key attributes that will help you thrive in this role.,