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0.0 years
0 Lacs
hyderabad, telangana, india
On-site
Key Responsibilities Complete ownership of individual circuit blocks in a DDR PHY design in cutting edge process technology nodes Responsible for circuit design, layout quality, electrical and timing analysis, and reliability checks Interface with cross-functional teams like RTL, Verification and Physical Design Preferred Experience Strong hands-on experience in DDR circuit designs in latest process technology nodes. Good technical knowledge of power-performance trade-offs in high-speed DDR and/or SerDes architectures Direct experience in all phases of design analysis including functional, static timing and electrical sign-off Strong understanding of the impact of variation on design perform...
Posted 2 days ago
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