2-7+ Years of experience in ASIC verification Should have tapped out atleast 1 chips from specs to post silicon debug Should have experience in creating testbenches from scratch Should have very good understanding of coverage driven verification closure Strong knowledge of Verilog, HVL (VERA or SystemVerilog or e (Specman)) Very good experience in writing scripts in Perl or Python or TCL Independent team player with excellent communication skills Knowledge of C++ Preference is given for students from IIT and NITs

2 to 7+ Years of experience in ASIC design Expertise in micro-architecture, design of design blocks (IP) to system-on-chip (SoC) components Experience in one/more of the following system bus interfaces like PCI Express, USB, SATA, SDIO, MIPI and /or AMBA. Knowledge of SVA Knowledge of memory controllers, CPU architecture is a plus Knowledge of considerations for performance, power and cost optimization is desirable Looking for highly motivated individuals and ability to deal with ambiguity Ability to work in a team environment Good debugging and problem solving skills Ability to work with external technology companies for combined development of SOCs Strong knowledge of Verilog Very good experience in writing scripts in Perl or Python or TCL Independent team player with excellent communication skills