Principal/Staff Circuit Engineer

You are an experienced and highly motivated Power-Management/PLL Circuit Engineer with over 10 years of experience in power management and PLL circuit design. Your role will involve leading the design and development of advanced power management and Phase-Locked Loop (PLL) circuits IPs for complex SoCs. As a Principal/Staff Circuit Engineer specializing in PMIC/Clock IC, you will be responsible for designing and developing power management circuits such as voltage regulators, DC-DC converters (PWM/PFM), and LDOs with features like Ultra-low noise, Capless, and Fast-transient architecture. Additionally, you will design high-performance PLL circuits for frequency synthesis and clock generation. Your daily tasks will include conducting detailed circuit simulations and analysis to optimize performance and ensure design robustness. You will collaborate with layout engineers to guide physical design and ensure optimal circuit performance. Furthermore, you will perform lab testing and characterization of power management and PLL circuits, as well as mentor junior engineers and provide technical guidance and support. Your qualifications should include a Bachelor's or Master's degree in Electrical Engineering or a related field, along with in-depth knowledge of analog and mixed-signal circuit design principles. You should have a strong understanding of power electronics and control systems, as well as proficiency in using circuit simulation tools such as Cadence and Spectre. Experience with lab equipment for circuit testing and characterization is also required. If you are excited about this opportunity and feel that you possess most of the qualifications listed, we encourage you to apply. Your skills and experience may align well with the role, and we believe you could be the right candidate for this position. For further details or to apply, please contact mohammed.zeeshan@nityo.com.,