Hot Vacancy Design Verification Engineer (5–10 Years) Location: Bangalore Experience: 5 to 10 Years Industry: Semiconductors / VLSI / ASIC Employment Type: Full Time Joining: Immediate to 30 days preferred Job Description: We are actively hiring skilled and passionate Design Verification Engineers with 5–10 years of experience for multiple cutting-edge SoC/ASIC. Roles and Responsibilities: Develop test plans , testbenches , and testcases using System Verilog and UVM . Own block-level and/or SoC-level verification and drive coverage closure . Verify protocols and interfaces such as AXI, AHB, PCIe, LPDDR5, UCIe, I3C, CXL , etc. Perform assertion-based verification (SVA) and support gate-level simulations (GLS) . Collaborate with cross-functional teams including RTL. Desired Candidate Profile: 5–10 years of hands-on experience in ASIC/SoC functional verification . Strong in System Verilog, UVM . B.E./B.Tech or M.E./M.Tech in ECE/EEE/CSE or related fields. Why Join Us? Work on next-gen chip designs with global teams. Opportunity to work on latest protocols and IPs . Interested Candidates share your resumes to priya@maxvytech.com and hr@maxvytech.com

Job Description: We are looking for a Senior RTL Design Engineer with solid experience in ASIC Digital Design . The ideal candidate should possess strong expertise in RTL design using Verilog/System Verilog , with a proven background in developing complex digital designs and working on high-speed interfaces. This is a pure design-focused role ; candidates with FPGA-centric experience will not be considered . Key Responsibilities: Develop and implement RTL designs using Verilog/System Verilog . Work on SoC and IP-level designs focused on high-speed interfaces (e.g., APB, AXI, AHB, DDR, PCIe). Perform lint , CDC , RDC checks and validate timing constraints. Support post-silicon validation . Use EDA tools for simulation, synthesis, and timing analysis. Required Qualifications: Minimum 8 years of hands-on experience in ASIC RTL/Digital Design . Strong expertise in Verilog and System Verilog . Working knowledge of high-speed bus protocols: APB, AXI, AHB, DDR, PCIe . Proficient with industry-standard EDA tools . Good understanding and experience with static checks . Must have experience in ASIC Design only FPGA-focused candidates will not be considered . Interested Candidates share your resumes to priya@maxvytech.com

Verification Engineer Location: Bengaluru Experience: 3+ Years Employment Type: Full-time Job Responsibilities: Create and carry out detailed plans to verify SoC systems. Design and manage test benches using SystemVerilog and UVM. Test the functionality, performance, and low-power aspects of designs. Identify and fix any design or verification problems on your own. Work with high-speed communication protocols like AXI, PCIe, Ethernet, CXL, and UCIe. Make sure that the design is thoroughly tested and follows the specifications. Skills Required: At least 3 years of experience in verifying SoC systems. Strong knowledge of SystemVerilog, UVM, and scripting languages like Python or Perl. Experience with simulation tools like VCS, Cadence, or Synopsys. Good understanding of communication protocols like AXI, PCIe, and Ethernet. Good problem-solving and analytical skills. Preferred Skills: Experience with UCIe (Universal Chiplet Interconnect Express) protocol is a plus. Interested candidates can share their resume to priya@maxvytech.com