Manager - DFT Engineering

Location: Bangalore, India
Employment Type: Full-Time
Experience: 5–12 Years
Salary: ₹15–50 LPA (Based on Experience and Technical Expertise)
Industry: Semiconductor / VLSI / ASIC / Chip Design

About the Role

We are hiring experienced DFT (Design for Testability) Engineers with strong hands-on expertise in semiconductor and SoC design projects.

The ideal candidate must have practical experience in ATPG (Automatic Test Pattern Generation) and GLS (Gate-Level Simulation), along with exposure to Scan Insertion, JTAG/IJTAG/Boundary Scan or MBIST.

This opportunity is suited for professionals with strong Core DFT implementation experience who can independently handle technical challenges, debugging and DFT-related project activities.

Key Responsibilities

• Perform ATPG pattern generation, fault simulation and pattern validation.
• Execute Gate-Level Simulation (GLS) and debug simulation failures.
• Work on Scan Insertion and Scan Architecture implementation.
• Handle JTAG, IJTAG and Boundary Scan implementation and verification.
• Perform MBIST insertion, simulation and debugging.
• Work on zero-delay and SDF timing simulations.
• Improve test coverage using Stuck-at, Transition Delay Faults (TDF) and IDDQ fault models.
• Work on SoC-level DFT implementation, including OCC/OPCG insertion and EDT/Test Compression Logic.
• Debug DFT issues using waveform analysis and industry-standard simulation tools.
• Collaborate with STA, Physical Design, Design Verification and cross-functional engineering teams.
• Provide technical guidance and mentoring to junior engineers for senior-level positions.

Mandatory Technical Skills

• ATPG – Automatic Test Pattern Generation
• GLS – Gate-Level Simulation

Both skills are mandatory and must involve hands-on project experience.

Additional DFT Skills

Candidates must have hands-on experience in at least one or more of the following:

• Scan Insertion / Scan Architecture
• JTAG / IJTAG / Boundary Scan
• MBIST (Memory Built-In Self-Test)

Candidates with approximately 5 years of experience should ideally have exposure to at least 3 of the 5 core DFT areas: ATPG, GLS, Scan Insertion, JTAG/IJTAG and MBIST.

Tools & Technologies

DFT Tools:

• Siemens Tessent
• Synopsys DFT Tools
• Cadence DFT Tools

Simulation Tools:

• Synopsys VCS
• Cadence NCSim
• Cadence Xcelium

Experience with fault simulation, waveform debugging, test coverage improvement and SDF simulations will be an advantage.

Preferred Candidate Background

• Semiconductor / VLSI / ASIC / SoC Design
• Chip Design and Semiconductor Engineering Services
• Core DFT Implementation Projects
• Experience with complex semiconductor design environments

Important Eligibility Criteria

• Strong hands-on experience in Core DFT is mandatory.
• ATPG and GLS experience is compulsory.
• Candidates should have actual DFT implementation experience.
• Good analytical, debugging and communication skills.
• Ability to work with cross-functional engineering teams.

Note: Candidates primarily experienced in ATE testing, post-silicon validation, hardware testing, board-level testing or silicon validation without hands-on Core DFT implementation will not be considered suitable for this position.

Interview Process

2–3 rounds of technical interviews (virtual), followed by an HR discussion.

Interested candidates can apply with their updated resumes.

If you have strong hands-on expertise in ATPG, GLS and Core DFT implementation, we would like to hear from you!

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Pay: ₹1,500,000.00 - ₹5,000,000.00 per year

Benefits:

• Health insurance
• Leave encashment
• Paid sick time
• Paid time off
• Provident Fund

Work Location: On the road