SoC Architect – Secure Computing Locations: Bangalore / Remote ( any where in India ) Job Description: We are seeking an experienced SoC Architect with a strong background in secure computing to help architect the next-generation AI inference SoC. You will focus on the definition and development of a secure I/O and compute subsystem, ensuring robustness from power-on to runtime in a virtualized, multi-tenant deployment. This role focuses on designing and integrating security features such as Root of Trust (RoT), secure boot and firmware upgrades, key lifecycle management, encryption engines, and isolation mechanisms at both the firmware and hardware layers. You will define and drive architectural specifications for secure PCIe interfaces, memory encryption support (e.g., for LPDDR or HBM), and establishing chain of trust between RISC- V cores. Responsibilities: • Define and develop secure boot flows, authentication, and RoT frameworks for PCIe-based AI accelerator cards. • Define and develop the verification plan for the secure sub-system of the SoC including but not limited to secure boot, firmware upgrade, key lifecycle management, and threat vector modeling. • Architect SoC-level and IP-level protections, including memory encryption and secure debug interfaces. • Integrate security-specific IPs such as crypto engines, key managers, and security monitors/sensors. • Collaborate with firmware, system software, and verification teams to ensure secure HW/SW co-design • Ensure compliance with security standards and best practices (e.g., NIST, FIPS, PSA Certified). • Participate in silicon bring-up and validation of secure features. Required Background: • BS/MS/Ph.D. in EE, CS, or related field with 10-25+ years of SoC design experience.• Strong knowledge of hardware security architecture, trusted execution environments, and secure memory. • Experience with secure boot flows, key provisioning, secure debug/test interfaces. • Familiarity with PCIe Gen 4/5, SR-IOV, and secure virtualization mechanisms. • Experience with RISC-V SoCs and integrating security features into SoC-level designs. • SystemVerilog and UVM-based verification experience a plus. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"
SoC Architect – Chiplet-Based Systems Locations: Bangalore / Remote (Any where in India ) Job Description: SoC Architect – Chiplet-Based Systems Job Description: Join us as a SoC Architect focusing on chiplet-based AI systems. You will help define and drive the architecture of modular compute platforms using chiplet integration. The position centers around architecting high-bandwidth I/O and memory connectivity between chiplets, ensuring efficient partitioning of functionality, and defining scalable inter-chiplet protocols for future-generation AI accelerators. This role involves working closely with packaging, PHY, and interconnect experts to define die-to-die interfaces (e.g., UCIe, BoW, or custom links) and orchestrating integration across logic, memory, and I/O chiplets. You’ll also own subsystem architecture for PCIe, RISC-V clusters, and memory hierarchies, while ensuring coherence and latency/power-optimized communication between disaggregated components. Responsibilities: • Define the SoC architecture for chiplet-based AI inference platforms, including inter-chiplet data paths, protocols, and synchronization strategies. • Drive partitioning decisions between compute, I/O, memory, and control chiplets. • Architect PCIe and DMA interfaces that interact with host systems and bridge to chiplet domains. • Specify die-to-die interconnect requirements (e.g., bandwidth, latency, power) and collaborate with packaging and PHY teams. • Integrate and verify third-party IPs for I/O, memory, and inter-chip communication. • Support bring-up and debug of multi-chip systems. Required Background: • BS/MS/Ph.D. in EE or CS with 10-25+ years of SoC or multi-die system experience. • Hands-on experience in chiplet-based design, including familiarity with UCIe, EMIB, Foveros, or similar packaging technologies. • Strong understanding of modular SoC partitioning and die-to-die interconnect architectures. • Experience in PCIe Gen 4/5, RISC-V subsystems, and high-performance memory interfaces (LPDDR4/5, HBM). • Familiarity with chiplet-aware system bring-up and verification methodologies. • SystemVerilog/UVM experience and knowledge of system-level test/debug strategies. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"
SoC Architect – Secure Computing Locations: Bangalore / Remote ( Any where in India ) Job Description: We are seeking an experienced SoC Architect with a strong background in secure computing to help architect the next-generation AI inference SoC. You will focus on the definition and development of a secure I/O and compute subsystem, ensuring robustness from power-on to runtime in a virtualized, multi-tenant deployment. This role focuses on designing and integrating security features such as Root of Trust (RoT), secure boot and firmware upgrades, key lifecycle management, encryption engines, and isolation mechanisms at both the firmware and hardware layers. You will define and drive architectural specifications for secure PCIe interfaces, memory encryption support (e.g., for LPDDR or HBM), and establishing chain of trust between RISC- V cores. Responsibilities: • Define and develop secure boot flows, authentication, and RoT frameworks for PCIe-based AI accelerator cards. • Define and develop the verification plan for the secure sub-system of the SoC including but not limited to secure boot, firmware upgrade, key lifecycle management, and threat vector modeling. • Architect SoC-level and IP-level protections, including memory encryption and secure debug interfaces. • Integrate security-specific IPs such as crypto engines, key managers, and security monitors/sensors. • Collaborate with firmware, system software, and verification teams to ensure secure HW/SW co-design • Ensure compliance with security standards and best practices (e.g., NIST, FIPS, PSA Certified). • Participate in silicon bring-up and validation of secure features. Required Background: • BS/MS/Ph.D. in EE, CS, or related field with 10-25+ years of SoC design experience.• Strong knowledge of hardware security architecture, trusted execution environments, and secure memory. • Experience with secure boot flows, key provisioning, secure debug/test interfaces. • Familiarity with PCIe Gen 4/5, SR-IOV, and secure virtualization mechanisms. • Experience with RISC-V SoCs and integrating security features into SoC-level designs. • SystemVerilog and UVM-based verification experience a plus. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"
Senior Simulation Architect Locations: Bangalore / Remote (Any where in India ) Job Description: Simulation Architect We are looking for a Simulation Architect to lead the design, development, and optimization of our C++ NPU architecture simulator, including creation of scalable multi- core simulation model. This role is critical to enabling our architecture, performance, hardware, and software teams to explore current- and next-generation NPU designs. You will lead the architecture simulator’s infrastructure, performance, scalability, and usability, ensuring it serves as a robust platform for both architecture exploration, hardware implementation and verification, and workload performance analysis. You’ll work closely with architects, designers, and software engineers to evolve the simulator into a world- class infrastructure supporting future product designs. Key Responsibilities • Architecture Simulator Infrastructure Leadership Design, maintain, and evolve the NPU simulator framework to ensure its performance, scalability, and reliability • Performance Optimization Profile and improve simulator runtime performance to accelerate design iteration and enable larger and more complex workloads using multiple threads/cores • Scalability Architect and implement multi-NPU simulation model, including modeling of inter- NPU communication, synchronization and shared or distributed memory systems • Developer Enablement Build infrastructure and APIs that make it easy for (a) architects and other simulator developers to add new components and features, and (b) hardware designers and verification engineers to gather necessary implementation details • User Experience Tools Develop supporting tools, scripts, and automation to simplify workload analysis and information gathering • Cross-Team collaboration Partner with architects, performance analysts, and software engineers to define requirements and prioritize improvements Required Background • Strong software engineering background, with expertise in C++, Python, and scalable simulation frameworks• Experience in developing or maintaining hardware architecture or performance simulators • Experience with parallel programming models such as pthreads and MPI • Strong system design and debugging skills • Familiarity with performance profiling, parallelization, and simulation optimization techniques • Excellent communication and collaboration skills across multi-disciplinary teams Nice to Have • Experience in NPU, GPU, or AI accelerator architecture • Familiarity with machine learning workloads Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"
SoC Architect – Chiplet-Based Systems Locations: Bangalore /Remote ( any where India ) Job Description: SoC Architect – Chiplet-Based Systems Job Description: Join us as a SoC Architect focusing on chiplet-based AI systems. You will help define and drive the architecture of modular compute platforms using chiplet integration. The position centers around architecting high-bandwidth I/O and memory connectivity between chiplets, ensuring efficient partitioning of functionality, and defining scalable inter-chiplet protocols for future-generation AI accelerators. This role involves working closely with packaging, PHY, and interconnect experts to define die-to-die interfaces (e.g., UCIe, BoW, or custom links) and orchestrating integration across logic, memory, and I/O chiplets. You’ll also own subsystem architecture for PCIe, RISC-V clusters, and memory hierarchies, while ensuring coherence and latency/power-optimized communication between disaggregated components. Responsibilities: • Define the SoC architecture for chiplet-based AI inference platforms, including inter-chiplet data paths, protocols, and synchronization strategies. • Drive partitioning decisions between compute, I/O, memory, and control chiplets. • Architect PCIe and DMA interfaces that interact with host systems and bridge to chiplet domains. • Specify die-to-die interconnect requirements (e.g., bandwidth, latency, power) and collaborate with packaging and PHY teams. • Integrate and verify third-party IPs for I/O, memory, and inter-chip communication. • Support bring-up and debug of multi-chip systems. Required Background: • BS/MS/Ph.D. in EE or CS with 10-25+ years of SoC or multi-die system experience. • Hands-on experience in chiplet-based design, including familiarity with UCIe, EMIB, Foveros, or similar packaging technologies. • Strong understanding of modular SoC partitioning and die-to-die interconnect architectures. • Experience in PCIe Gen 4/5, RISC-V subsystems, and high-performance memory interfaces (LPDDR4/5, HBM). • Familiarity with chiplet-aware system bring-up and verification methodologies. • SystemVerilog/UVM experience and knowledge of system-level test/debug strategies. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"
Senior Verification Director Bangalore Job Title: Senior Director, SoC & IP Verification We are a well-funded US AI hardware startup building next-generation compute platforms that bring advanced, secure, and sustainable AI from the edge to the cloud. Backed by groundbreaking R&D in computation physics, ultra-efficient circuits, and scalable architectures, we are redefining what’s possible in performance and energy efficiency. Join a team of industry veterans pushing the boundaries of AI and shaping technology that will serve humanity at global scale. Job Description: We are seeking a Senior Director of Digital Hardware Verification to lead and expand our SoC design verification organization in Bangalore. This is a hands-on technical leadership role responsible for scaling a world-class design verification team, driving verification across multiple SoC programs, and collaborating closely with architecture, RTL design, physical design, firmware, and software teams. You will play a pivotal role in driving verifying for ultra-efficient, next-generation AI compute platforms. Responsibilities Lead and mentor a high-performing team of SoC design verification engineers across IP verification, SoC/subsystem verification and platform verification. Own IP, subsystem, and full-chip design verification from spec through tape-out. Partner closely with Architecture, RTL design, PD, Firmware, and Post-Si teams to realize high-quality silicon on aggressive schedules. Drive project planning, resourcing, task allocation, and execution tracking for verification teams across multiple concurrent programs. Recruit, develop, and retain top-tier engineering talent. Establish and enforce best practices for design verification to achieve high quality designs Develop design verification architecture, test plans and other verification documents. Plan for coverage and other quality metrics. Guide and oversee test bench components, checker, monitor, scoreboard development, low-power verification, equivalence checking, hardware prototyping and other verification technique. Participate in design, micro-architecture, DV, and PD reviews to ensure there are no gaps in design verification. Coordinate seamlessly with global teams across geographies to ensure verification convergence and alignment. Requirements Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. 20–25 years of experience in SoC/ASIC development with at least 8+ years in technical leadership or engineering management. Proven expertise in front-end design verification using UVM or other such verification frameworks. Deep expertise in coverage driven verification, equivalence checking, hardware prototyping for verification, and other state of the art verification methodologies. Broad experience with SoC and full chip verification, clock/power/reset verification, low power verification system bring up and firmware verification. Experience with UCIe or similar chiplet protocols, PCIe and/or CXL. Good understanding of interconnect protocols (AXI/CHI), memory systems (DDR, HBM), and caching/coherency architectures. Experience with ML/AI accelerators, GPUs, CPUs (RISC-V or ARM), and advanced low-power design techniques. Some experience in front-end micro-architecture and RTL design is a big plus. Exceptional communication, leadership, and cross-functional collaboration skills. Experience leading and collaborating with geographically distributed teams. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"
Senior Verification Director Bangalore Job Title: Senior Director, SoC & IP Verification We are a well-funded US AI hardware startup building next-generation compute platforms that bring advanced, secure, and sustainable AI from the edge to the cloud. Backed by groundbreaking R&D in computation physics, ultra-efficient circuits, and scalable architectures, we are redefining what’s possible in performance and energy efficiency. Join a team of industry veterans pushing the boundaries of AI and shaping technology that will serve humanity at global scale. Job Description: We are seeking a Senior Director of Digital Hardware Verification to lead and expand our SoC design verification organization in Bangalore. This is a hands-on technical leadership role responsible for scaling a world-class design verification team, driving verification across multiple SoC programs, and collaborating closely with architecture, RTL design, physical design, firmware, and software teams. You will play a pivotal role in driving verifying for ultra-efficient, next-generation AI compute platforms. Responsibilities Lead and mentor a high-performing team of SoC design verification engineers across IP verification, SoC/subsystem verification and platform verification. Own IP, subsystem, and full-chip design verification from spec through tape-out. Partner closely with Architecture, RTL design, PD, Firmware, and Post-Si teams to realize high-quality silicon on aggressive schedules. Drive project planning, resourcing, task allocation, and execution tracking for verification teams across multiple concurrent programs. Recruit, develop, and retain top-tier engineering talent. Establish and enforce best practices for design verification to achieve high quality designs Develop design verification architecture, test plans and other verification documents. Plan for coverage and other quality metrics. Guide and oversee test bench components, checker, monitor, scoreboard development, low-power verification, equivalence checking, hardware prototyping and other verification technique. Participate in design, micro-architecture, DV, and PD reviews to ensure there are no gaps in design verification. Coordinate seamlessly with global teams across geographies to ensure verification convergence and alignment. Requirements Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. 20–25 years of experience in SoC/ASIC development with at least 8+ years in technical leadership or engineering management. Proven expertise in front-end design verification using UVM or other such verification frameworks. Deep expertise in coverage driven verification, equivalence checking, hardware prototyping for verification, and other state of the art verification methodologies. Broad experience with SoC and full chip verification, clock/power/reset verification, low power verification system bring up and firmware verification. Experience with UCIe or similar chiplet protocols, PCIe and/or CXL. Good understanding of interconnect protocols (AXI/CHI), memory systems (DDR, HBM), and caching/coherency architectures. Experience with ML/AI accelerators, GPUs, CPUs (RISC-V or ARM), and advanced low-power design techniques. Some experience in front-end micro-architecture and RTL design is a big plus. Exceptional communication, leadership, and cross-functional collaboration skills. Experience leading and collaborating with geographically distributed teams. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"
Vice President of Hardware Bangalore We are a well-funded US AI hardware startup building next-generation compute platforms that bring advanced, secure, and sustainable AI from the edge to the cloud. Backed by groundbreaking R&D in computation physics, ultra-efficient circuits, and scalable architectures, we are redefining what’s possible in performance and energy efficiency. Join a team of industry veterans pushing the boundaries of AI and shaping technology that will serve humanity at global scale. Title/Role: Vice President of Hardware at , India. Description: We are a leader in advanced AI hardware and software systems for edge-to-cloud computing. our robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. Overview: We are looking for a dynamic leader who will play a critical role in establishing and driving the buildout of its India hardware organization. Reporting directly to the C-suite, this individual will lead efforts to recruit a world-class team of hardware and firmware engineers, technical leaders, and executives; oversee technical and strategic operations in India; work with the global leadership team to drive strategic growth domestically and globally; and serve as the primary liaison between the India organization and the rest of global leadership. The ideal candidate is a seasoned executive with a strong background in technology, silicon chip design, software, team building, and operations management. Key Responsibilities: Team Building & Leadership: • Develop and execute a comprehensive strategy to establish presence in India. • Recruit top talent across technical (hardware and firmware), operational, and additional support functions to build a high-performing India team. • Establish the AI silicon team for in India, focusing on acquiring top talent across Analog Design, Architecture, Digital Design, Digital Verification (DV), Physical Design, and Bring-up. • Foster a collaborative and innovative culture that aligns with global values. Technical Leadership Growth: • Grow technical teams that can contribute to our roadmap and hardware & software products. • Engage deeply in the development and definition of foundational chip architectures , to be well positioned to define and drive future product opportunities. • Lead the India team to collaborate jointly with team-members across world-wide sites with the objective of enabling multiple product and test-chip silicon tapeouts. We are expected to have at least 1 tapeout every year for the next few years – as we ramp up silicon products across different technology nodes and markets. • Building out our IP portfolio across multiple technology nodes – enabling us to license key technologies to adjacent markets including automotive, AR/VR/XR, IoT and datacenters. Technical Execution of Physical Design and Verification (optional in case of PDexpertise): • Drive technical execution across the entire ASIC design flow with specific emphasis on Physical design • Establish physical design methodologies, flow automation, chip floorplan, power/clock distribution, chip assembly and P&R, timing closure • Oversee physical implementation, physical verification, timing closure, documentation and tapeout of complex high performance mixed-signal SOCs (System on a Chip). • Managing PD resources (employees and contractors), to deliver on aggressive tapeout schedules. • Collaborate with a cross-disciplined, multi-site team to identify the issues, get buyin on proposed solutions, and implement the solutions in time for the team to execute to schedule . Qualification and skills: • Hold a BSEE (MSEE preferred) or equivalent experience • 25+ years of experience in large VLSI physical design implementation with exposure to advanced nodes down to 3nm technology. • Successful track record of delivering designs to high volume production. • Familiarity with industry standard P&R, Timing analysis, Physical Verification and IR Drop Analysis CAD tools from Synopsys (ICC2/DC/PT/STAR-RC/ICV), Cadence (Innovus, Tempus, Voltus ) and/or Mentor Graphics. • Experience with the integration of custom analog IP macros such as Serdes, custom memories, CAMs, high-speed IO drivers, PLLs etc. • Confirmed prior experience in timing closure, clock/power distribution and analysis, RC extraction and correlation, place/ route and tapeout solutions. • Strong analytical and debugging skills required • Deep understanding of low power implementation initiatives and techniques. Operational Management: • Oversee all aspects of India operations, including office setup, infrastructure, compliance, and vendor management. • Ensure efficient and effective operational processes to support business goals and maintain global alignment. • Develop and manage budgets, ensuring cost efficiency and financial accountability. Strategic Growth: • Identify and pursue growth opportunities in India’s AI and semiconductor ecosystems. • Collaborate with global leadership to align India’s strategic initiatives with corporate objectives. • Represent us in industry events, fostering partnerships and enhancing brand presence in India. Stakeholder Engagement: • Serve as the primary point of contact for India operations with regular updates to global leadership. • Build relationships with government entities, industry bodies, and academic institutions to support growth and talent acquisition. • Navigate India’s regulatory and business landscape, ensuring compliance with all applicable laws and standards. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"
Senior Vice President of Hardware Bangalore We are a well-funded US AI hardware startup building next-generation compute platforms that bring advanced, secure, and sustainable AI from the edge to the cloud. Backed by groundbreaking R&D in computation physics, ultra-efficient circuits, and scalable architectures, we are redefining what’s possible in performance and energy efficiency. Join a team of industry veterans pushing the boundaries of AI and shaping technology that will serve humanity at global scale. Title/Role: Vice President of Hardware at , India. Description: We are a leader in advanced AI hardware and software systems for edge-to-cloud computing. our robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. Overview: We are looking for a dynamic leader who will play a critical role in establishing and driving the buildout of its India hardware organization. Reporting directly to the C-suite, this individual will lead efforts to recruit a world-class team of hardware and firmware engineers, technical leaders, and executives; oversee technical and strategic operations in India; work with the global leadership team to drive strategic growth domestically and globally; and serve as the primary liaison between the India organization and the rest of global leadership. The ideal candidate is a seasoned executive with a strong background in technology, silicon chip design, software, team building, and operations management. Key Responsibilities: Team Building & Leadership: • Develop and execute a comprehensive strategy to establish presence in India. • Recruit top talent across technical (hardware and firmware), operational, and additional support functions to build a high-performing India team. • Establish the AI silicon team for in India, focusing on acquiring top talent across Analog Design, Architecture, Digital Design, Digital Verification (DV), Physical Design, and Bring-up. • Foster a collaborative and innovative culture that aligns with global values. Technical Leadership Growth: • Grow technical teams that can contribute to our roadmap and hardware & software products. • Engage deeply in the development and definition of foundational chip architectures , to be well positioned to define and drive future product opportunities. • Lead the India team to collaborate jointly with team-members across world-wide sites with the objective of enabling multiple product and test-chip silicon tapeouts. We are expected to have at least 1 tapeout every year for the next few years – as we ramp up silicon products across different technology nodes and markets. • Building out our IP portfolio across multiple technology nodes – enabling us to license key technologies to adjacent markets including automotive, AR/VR/XR, IoT and datacenters. Technical Execution of Physical Design and Verification (optional in case of PDexpertise): • Drive technical execution across the entire ASIC design flow with specific emphasis on Physical design • Establish physical design methodologies, flow automation, chip floorplan, power/clock distribution, chip assembly and P&R, timing closure • Oversee physical implementation, physical verification, timing closure, documentation and tapeout of complex high performance mixed-signal SOCs (System on a Chip). • Managing PD resources (employees and contractors), to deliver on aggressive tapeout schedules. • Collaborate with a cross-disciplined, multi-site team to identify the issues, get buyin on proposed solutions, and implement the solutions in time for the team to execute to schedule . Qualification and skills: • Hold a BSEE (MSEE preferred) or equivalent experience • 27+ years of experience in large VLSI physical design implementation with exposure to advanced nodes down to 3nm technology. • Successful track record of delivering designs to high volume production. • Familiarity with industry standard P&R, Timing analysis, Physical Verification and IR Drop Analysis CAD tools from Synopsys (ICC2/DC/PT/STAR-RC/ICV), Cadence (Innovus, Tempus, Voltus ) and/or Mentor Graphics. • Experience with the integration of custom analog IP macros such as Serdes, custom memories, CAMs, high-speed IO drivers, PLLs etc. • Confirmed prior experience in timing closure, clock/power distribution and analysis, RC extraction and correlation, place/ route and tapeout solutions. • Strong analytical and debugging skills required • Deep understanding of low power implementation initiatives and techniques. Operational Management: • Oversee all aspects of India operations, including office setup, infrastructure, compliance, and vendor management. • Ensure efficient and effective operational processes to support business goals and maintain global alignment. • Develop and manage budgets, ensuring cost efficiency and financial accountability. Strategic Growth: • Identify and pursue growth opportunities in India’s AI and semiconductor ecosystems. • Collaborate with global leadership to align India’s strategic initiatives with corporate objectives. • Represent us in industry events, fostering partnerships and enhancing brand presence in India. Stakeholder Engagement: • Serve as the primary point of contact for India operations with regular updates to global leadership. • Build relationships with government entities, industry bodies, and academic institutions to support growth and talent acquisition. • Navigate India’s regulatory and business landscape, ensuring compliance with all applicable laws and standards. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"
Vice President of Hardware Bangalore We are a well-funded US AI hardware startup building next-generation compute platforms that bring advanced, secure, and sustainable AI from the edge to the cloud. Backed by groundbreaking R&D in computation physics, ultra-efficient circuits, and scalable architectures, we are redefining what’s possible in performance and energy efficiency. Join a team of industry veterans pushing the boundaries of AI and shaping technology that will serve humanity at global scale. Title/Role: Vice President of Hardware at , India. Description: We are a leader in advanced AI hardware and software systems for edge-to-cloud computing. our robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. Overview: We are looking for a dynamic leader who will play a critical role in establishing and driving the buildout of its India hardware organization. Reporting directly to the C-suite, this individual will lead efforts to recruit a world-class team of hardware and firmware engineers, technical leaders, and executives; oversee technical and strategic operations in India; work with the global leadership team to drive strategic growth domestically and globally; and serve as the primary liaison between the India organization and the rest of global leadership. The ideal candidate is a seasoned executive with a strong background in technology, silicon chip design, software, team building, and operations management. Key Responsibilities: Team Building & Leadership: • Develop and execute a comprehensive strategy to establish presence in India. • Recruit top talent across technical (hardware and firmware), operational, and additional support functions to build a high-performing India team. • Establish the AI silicon team for in India, focusing on acquiring top talent across Analog Design, Architecture, Digital Design, Digital Verification (DV), Physical Design, and Bring-up. • Foster a collaborative and innovative culture that aligns with global values. Technical Leadership Growth: • Grow technical teams that can contribute to our roadmap and hardware & software products. • Engage deeply in the development and definition of foundational chip architectures , to be well positioned to define and drive future product opportunities. • Lead the India team to collaborate jointly with team-members across world-wide sites with the objective of enabling multiple product and test-chip silicon tapeouts. We are expected to have at least 1 tapeout every year for the next few years – as we ramp up silicon products across different technology nodes and markets. • Building out our IP portfolio across multiple technology nodes – enabling us to license key technologies to adjacent markets including automotive, AR/VR/XR, IoT and datacenters. Technical Execution of Physical Design and Verification (optional in case of PDexpertise): • Drive technical execution across the entire ASIC design flow with specific emphasis on Physical design • Establish physical design methodologies, flow automation, chip floorplan, power/clock distribution, chip assembly and P&R, timing closure • Oversee physical implementation, physical verification, timing closure, documentation and tapeout of complex high performance mixed-signal SOCs (System on a Chip). • Managing PD resources (employees and contractors), to deliver on aggressive tapeout schedules. • Collaborate with a cross-disciplined, multi-site team to identify the issues, get buyin on proposed solutions, and implement the solutions in time for the team to execute to schedule . Qualification and skills: • Hold a BSEE (MSEE preferred) or equivalent experience • 25+ years of experience in large VLSI physical design implementation with exposure to advanced nodes down to 3nm technology. • Successful track record of delivering designs to high volume production. • Familiarity with industry standard P&R, Timing analysis, Physical Verification and IR Drop Analysis CAD tools from Synopsys (ICC2/DC/PT/STAR-RC/ICV), Cadence (Innovus, Tempus, Voltus ) and/or Mentor Graphics. • Experience with the integration of custom analog IP macros such as Serdes, custom memories, CAMs, high-speed IO drivers, PLLs etc. • Confirmed prior experience in timing closure, clock/power distribution and analysis, RC extraction and correlation, place/ route and tapeout solutions. • Strong analytical and debugging skills required • Deep understanding of low power implementation initiatives and techniques. Operational Management: • Oversee all aspects of India operations, including office setup, infrastructure, compliance, and vendor management. • Ensure efficient and effective operational processes to support business goals and maintain global alignment. • Develop and manage budgets, ensuring cost efficiency and financial accountability. Strategic Growth: • Identify and pursue growth opportunities in India’s AI and semiconductor ecosystems. • Collaborate with global leadership to align India’s strategic initiatives with corporate objectives. • Represent us in industry events, fostering partnerships and enhancing brand presence in India. Stakeholder Engagement: • Serve as the primary point of contact for India operations with regular updates to global leadership. • Build relationships with government entities, industry bodies, and academic institutions to support growth and talent acquisition. • Navigate India’s regulatory and business landscape, ensuring compliance with all applicable laws and standards. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"
Senior Vice President of Hardware Bangalore We are a well-funded US AI hardware startup building next-generation compute platforms that bring advanced, secure, and sustainable AI from the edge to the cloud. Backed by groundbreaking R&D in computation physics, ultra-efficient circuits, and scalable architectures, we are redefining what’s possible in performance and energy efficiency. Join a team of industry veterans pushing the boundaries of AI and shaping technology that will serve humanity at global scale. Title/Role: Vice President of Hardware at , India. Description: We are a leader in advanced AI hardware and software systems for edge-to-cloud computing. our robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. Overview: We are looking for a dynamic leader who will play a critical role in establishing and driving the buildout of its India hardware organization. Reporting directly to the C-suite, this individual will lead efforts to recruit a world-class team of hardware and firmware engineers, technical leaders, and executives; oversee technical and strategic operations in India; work with the global leadership team to drive strategic growth domestically and globally; and serve as the primary liaison between the India organization and the rest of global leadership. The ideal candidate is a seasoned executive with a strong background in technology, silicon chip design, software, team building, and operations management. Key Responsibilities: Team Building & Leadership: • Develop and execute a comprehensive strategy to establish presence in India. • Recruit top talent across technical (hardware and firmware), operational, and additional support functions to build a high-performing India team. • Establish the AI silicon team for in India, focusing on acquiring top talent across Analog Design, Architecture, Digital Design, Digital Verification (DV), Physical Design, and Bring-up. • Foster a collaborative and innovative culture that aligns with global values. Technical Leadership Growth: • Grow technical teams that can contribute to our roadmap and hardware & software products. • Engage deeply in the development and definition of foundational chip architectures , to be well positioned to define and drive future product opportunities. • Lead the India team to collaborate jointly with team-members across world-wide sites with the objective of enabling multiple product and test-chip silicon tapeouts. We are expected to have at least 1 tapeout every year for the next few years – as we ramp up silicon products across different technology nodes and markets. • Building out our IP portfolio across multiple technology nodes – enabling us to license key technologies to adjacent markets including automotive, AR/VR/XR, IoT and datacenters. Technical Execution of Physical Design and Verification (optional in case of PDexpertise): • Drive technical execution across the entire ASIC design flow with specific emphasis on Physical design • Establish physical design methodologies, flow automation, chip floorplan, power/clock distribution, chip assembly and P&R, timing closure • Oversee physical implementation, physical verification, timing closure, documentation and tapeout of complex high performance mixed-signal SOCs (System on a Chip). • Managing PD resources (employees and contractors), to deliver on aggressive tapeout schedules. • Collaborate with a cross-disciplined, multi-site team to identify the issues, get buyin on proposed solutions, and implement the solutions in time for the team to execute to schedule . Qualification and skills: • Hold a BSEE (MSEE preferred) or equivalent experience • 27+ years of experience in large VLSI physical design implementation with exposure to advanced nodes down to 3nm technology. • Successful track record of delivering designs to high volume production. • Familiarity with industry standard P&R, Timing analysis, Physical Verification and IR Drop Analysis CAD tools from Synopsys (ICC2/DC/PT/STAR-RC/ICV), Cadence (Innovus, Tempus, Voltus ) and/or Mentor Graphics. • Experience with the integration of custom analog IP macros such as Serdes, custom memories, CAMs, high-speed IO drivers, PLLs etc. • Confirmed prior experience in timing closure, clock/power distribution and analysis, RC extraction and correlation, place/ route and tapeout solutions. • Strong analytical and debugging skills required • Deep understanding of low power implementation initiatives and techniques. Operational Management: • Oversee all aspects of India operations, including office setup, infrastructure, compliance, and vendor management. • Ensure efficient and effective operational processes to support business goals and maintain global alignment. • Develop and manage budgets, ensuring cost efficiency and financial accountability. Strategic Growth: • Identify and pursue growth opportunities in India’s AI and semiconductor ecosystems. • Collaborate with global leadership to align India’s strategic initiatives with corporate objectives. • Represent us in industry events, fostering partnerships and enhancing brand presence in India. Stakeholder Engagement: • Serve as the primary point of contact for India operations with regular updates to global leadership. • Build relationships with government entities, industry bodies, and academic institutions to support growth and talent acquisition. • Navigate India’s regulatory and business landscape, ensuring compliance with all applicable laws and standards. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"
Job Title: Senior Director, Digital Hardware Design Bangalore We are a well-funded US AI hardware startup building next-generation compute platforms that bring advanced, secure, and sustainable AI from the edge to the cloud. Backed by groundbreaking R&D in computation physics, ultra-efficient circuits, and scalable architectures, we are redefining what’s possible in performance and energy efficiency. Join a team of industry veterans pushing the boundaries of AI and shaping technology that will serve humanity at global scale. Job Description: We are seeking a Senior Director of Digital Hardware Design to lead and expand our SoC design organization in Bangalore. This is a hands-on technical leadership role responsible for scaling a world-class front-end design team, driving execution across multiple SoC programs, and collaborating closely with architecture, verification, physical design, firmware, and software teams. You will play a pivotal role in defining and delivering ultra-efficient, next-generation AI compute platforms. Responsibilities Lead and mentor a high-performing team of SoC design engineers across RTL design, IP logic development, and SoC/subsystem integration. Own IP, subsystem, and full-chip design and integration from concept through tape-out. Partner closely with Architecture, DV, PD, Firmware, and Post-Si teams to deliver high-quality silicon on aggressive schedules. Drive project planning, resourcing, task allocation, and execution tracking for multiple concurrent programs. Recruit, develop, and retain top-tier engineering talent. Establish and enforce best practices for RTL development, design quality, verification readiness, low-power design, physical-awareness, and documentation. Participate in design, micro-architecture, DV, and PD reviews to ensure scalability, performance, and power/area efficiency. Coordinate seamlessly with global teams across geographies to ensure design convergence and alignment. Requirements Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. 20–25 years of experience in SoC/ASIC development with at least 8+ years in technical leadership or engineering management. Proven expertise in front-end RTL design using Verilog/SystemVerilog. Strong experience with UCIe or similar chiplet protocols, and PCIe and/or CXL. Deep understanding of interconnect protocols (AXI/CHI), memory systems (DDR, HBM), and caching/coherency architectures. Broad experience with SoC integration, clock/power/reset domains, and IP/PHY integration. Experience with ML/AI accelerators, GPUs, CPUs (RISC-V or ARM), and advanced low-power design techniques. Familiarity with synthesis, STA, design constraints, and physical-design handoff requirements. Strong understanding of the full silicon development lifecycle from architecture/spec through GDS/tape-out. Exceptional communication, leadership, and cross-functional collaboration skills. Experience leading and collaborating with geographically distributed teams. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"
Job Title: Senior Director, Digital Hardware Design Bangalore We are a well-funded US AI hardware startup building next-generation compute platforms that bring advanced, secure, and sustainable AI from the edge to the cloud. Backed by groundbreaking R&D in computation physics, ultra-efficient circuits, and scalable architectures, we are redefining what’s possible in performance and energy efficiency. Join a team of industry veterans pushing the boundaries of AI and shaping technology that will serve humanity at global scale. Job Description: We are seeking a Senior Director of Digital Hardware Design to lead and expand our SoC design organization in Bangalore. This is a hands-on technical leadership role responsible for scaling a world-class front-end design team, driving execution across multiple SoC programs, and collaborating closely with architecture, verification, physical design, firmware, and software teams. You will play a pivotal role in defining and delivering ultra-efficient, next-generation AI compute platforms. Responsibilities Lead and mentor a high-performing team of SoC design engineers across RTL design, IP logic development, and SoC/subsystem integration. Own IP, subsystem, and full-chip design and integration from concept through tape-out. Partner closely with Architecture, DV, PD, Firmware, and Post-Si teams to deliver high-quality silicon on aggressive schedules. Drive project planning, resourcing, task allocation, and execution tracking for multiple concurrent programs. Recruit, develop, and retain top-tier engineering talent. Establish and enforce best practices for RTL development, design quality, verification readiness, low-power design, physical-awareness, and documentation. Participate in design, micro-architecture, DV, and PD reviews to ensure scalability, performance, and power/area efficiency. Coordinate seamlessly with global teams across geographies to ensure design convergence and alignment. Requirements Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. 20–25 years of experience in SoC/ASIC development with at least 8+ years in technical leadership or engineering management. Proven expertise in front-end RTL design using Verilog/SystemVerilog. Strong experience with UCIe or similar chiplet protocols, and PCIe and/or CXL. Deep understanding of interconnect protocols (AXI/CHI), memory systems (DDR, HBM), and caching/coherency architectures. Broad experience with SoC integration, clock/power/reset domains, and IP/PHY integration. Experience with ML/AI accelerators, GPUs, CPUs (RISC-V or ARM), and advanced low-power design techniques. Familiarity with synthesis, STA, design constraints, and physical-design handoff requirements. Strong understanding of the full silicon development lifecycle from architecture/spec through GDS/tape-out. Exceptional communication, leadership, and cross-functional collaboration skills. Experience leading and collaborating with geographically distributed teams. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"
Senior Simulation Architect Locations: Bangalore / Remote (Any where in India ) Job Description: Simulation Architect We are looking for a Simulation Architect to lead the design, development, and optimization of our C++ NPU architecture simulator, including creation of scalable multi- core simulation model. This role is critical to enabling our architecture, performance, hardware, and software teams to explore current- and next-generation NPU designs. You will lead the architecture simulator’s infrastructure, performance, scalability, and usability, ensuring it serves as a robust platform for both architecture exploration, hardware implementation and verification, and workload performance analysis. You’ll work closely with architects, designers, and software engineers to evolve the simulator into a world- class infrastructure supporting future product designs. Key Responsibilities • Architecture Simulator Infrastructure Leadership Design, maintain, and evolve the NPU simulator framework to ensure its performance, scalability, and reliability • Performance Optimization Profile and improve simulator runtime performance to accelerate design iteration and enable larger and more complex workloads using multiple threads/cores • Scalability Architect and implement multi-NPU simulation model, including modeling of inter- NPU communication, synchronization and shared or distributed memory systems • Developer Enablement Build infrastructure and APIs that make it easy for (a) architects and other simulator developers to add new components and features, and (b) hardware designers and verification engineers to gather necessary implementation details • User Experience Tools Develop supporting tools, scripts, and automation to simplify workload analysis and information gathering • Cross-Team collaboration Partner with architects, performance analysts, and software engineers to define requirements and prioritize improvements Required Background • Strong software engineering background, with expertise in C++, Python, and scalable simulation frameworks• Experience in developing or maintaining hardware architecture or performance simulators • Experience with parallel programming models such as pthreads and MPI • Strong system design and debugging skills • Familiarity with performance profiling, parallelization, and simulation optimization techniques • Excellent communication and collaboration skills across multi-disciplinary teams Nice to Have • Experience in NPU, GPU, or AI accelerator architecture • Familiarity with machine learning workloads Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"
Senior Simulation Architect Locations: Bangalore / Remote (Any where in India ) Job Description: Simulation Architect We are looking for a Simulation Architect to lead the design, development, and optimization of our C++ NPU architecture simulator, including creation of scalable multi- core simulation model. This role is critical to enabling our architecture, performance, hardware, and software teams to explore current- and next-generation NPU designs. You will lead the architecture simulator's infrastructure, performance, scalability, and usability, ensuring it serves as a robust platform for both architecture exploration, hardware implementation and verification, and workload performance analysis. You'll work closely with architects, designers, and software engineers to evolve the simulator into a world- class infrastructure supporting future product designs. Key Responsibilities Architecture Simulator Infrastructure Leadership Design, maintain, and evolve the NPU simulator framework to ensure its performance, scalability, and reliability Performance Optimization Profile and improve simulator runtime performance to accelerate design iteration and enable larger and more complex workloads using multiple threads/cores Scalability Architect and implement multi-NPU simulation model, including modeling of inter- NPU communication, synchronization and shared or distributed memory systems Developer Enablement Build infrastructure and APIs that make it easy for (a) architects and other simulator developers to add new components and features, and (b) hardware designers and verification engineers to gather necessary implementation details User Experience Tools Develop supporting tools, scripts, and automation to simplify workload analysis and information gathering Cross-Team collaboration Partner with architects, performance analysts, and software engineers to define requirements and prioritize improvements Required Background Strong software engineering background, with expertise in C++, Python, and scalable simulation frameworks Experience in developing or maintaining hardware architecture or performance simulators Experience with parallel programming models such as pthreads and MPI Strong system design and debugging skills Familiarity with performance profiling, parallelization, and simulation optimization techniques Excellent communication and collaboration skills across multi-disciplinary teams Nice to Have Experience in NPU, GPU, or AI accelerator architecture Familiarity with machine learning workloads Contact: Uday Mulya Technologies [HIDDEN TEXT] Mining The Knowledge Community
Senior Physical Design Director Bangalore We are a well-funded US AI hardware startup building next-generation compute platforms that bring advanced, secure, and sustainable AI from the edge to the cloud. Backed by groundbreaking R&D in computation physics, ultra-efficient circuits, and scalable architectures, we are redefining what’s possible in performance and energy efficiency. Join a team of industry veterans pushing the boundaries of AI and shaping technology that will serve humanity at global scale. and serve as the primary liaison between the India organization and the rest of global leadership. The ideal candidate is a seasoned executive with a strong background in technology, silicon chip design, software, team building, and operations management. Key Responsibilities: Team Building & Leadership: • Develop and execute a comprehensive strategy to establish presence in India. • Recruit top talent • Establish the AI silicon team for in India, focusing on acquiring top talent across , Physical Design, • Foster a collaborative and innovative culture that aligns with global values. Technical Leadership Growth: • Grow technical teams that can contribute to our roadmap and hardware & software products. • Engage deeply in the development and definition of foundational chip architectures , to be well positioned to define and drive future product opportunities. • Lead the India team to collaborate jointly with team-members across world-wide sites with the objective of enabling multiple product and test-chip silicon tapeouts. We are expected to have at least 1 tapeout every year for the next few years – as we ramp up silicon products across different technology nodes and markets. • Building out our IP portfolio across multiple technology nodes – enabling us to license key technologies to adjacent markets including automotive, AR/VR/XR, IoT and datacenters. Technical Execution of Physical Design and Verification (optional in case of PDexpertise): • Drive technical execution across the entire ASIC design flow with specific emphasis on Physical design • Establish physical design methodologies, flow automation, chip floorplan, power/clock distribution, chip assembly and P&R, timing closure • Oversee physical implementation, physical verification, timing closure, documentation and tapeout of complex high performance mixed-signal SOCs (System on a Chip). • Managing PD resources (employees and contractors), to deliver on aggressive tapeout schedules. • Collaborate with a cross-disciplined, multi-site team to identify the issues, get buyin on proposed solutions, and implement the solutions in time for the team to execute to schedule . Qualification and skills: • Hold a BSEE (MSEE preferred) or equivalent experience • 20+ years of experience in large VLSI physical design implementation with exposure to advanced nodes down to 3nm technology. • Successful track record of delivering designs to high volume production. • Familiarity with industry standard P&R, Timing analysis, Physical Verification and IR Drop Analysis CAD tools from Synopsys (ICC2/DC/PT/STAR-RC/ICV), Cadence (Innovus, Tempus, Voltus ) and/or Mentor Graphics. • Experience with the integration of custom analog IP macros such as Serdes, custom memories, CAMs, high-speed IO drivers, PLLs etc. • Confirmed prior experience in timing closure, clock/power distribution and analysis, RC extraction and correlation, place/ route and tapeout solutions. • Strong analytical and debugging skills required • Deep understanding of low power implementation initiatives and techniques. Operational Management: • Oversee all aspects of India operations, including office setup, infrastructure, compliance, and vendor management. • Ensure efficient and effective operational processes to support business goals and maintain global alignment. • Develop and manage budgets, ensuring cost efficiency and financial accountability. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community"