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CPU Physical Design Engineer

4 - 9 years

12 - 16 Lacs

Bengaluru

Posted:3 months ago| Platform: Naukri logo

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Skills Required

python physical design static timing analysis vhdl floorplan sd routing drc perl tcl cmos synthesis sta primetime lvs timing analysis cadence verilog physical verification floor planning signal integrity timing closure pnr synopsys placement

Work Mode

Work from Office

Job Type

Full Time

Job Description

You will be part of ACE India , in the P- Core design team driving Intel's latest CPU's in the latest process technology. In this position, you will be responsible for timing analysis and convergence of complex partitions. Your responsibilities will include but not limited to: 1. Responsible for timing execution and convergence including setup and hold for over 5GHz Freq and low-power digital designs. 2. Deep understanding of Static timing analysis concepts 3. Timing Convergence across all HVM targets4. Closely work with SD, Integration and Floor plan teams Qualifications You must possess a Masters Degree in Electrical or Electronics Engineering with at least 4 or more years of experience in related field or a Bachelor's Degree with at least 6 years of experience. Technical Expertise in Static Timing Analysis is preferred. Preferred additional skills :- Experience of handle complex core design, high-speed designs - Timing signoff flows/tools experience both/either Synopsys/Cadence tools - Very good knowledge on Timing tools, flows and methodology - Ability to handle new feature feasibility studies - SD flow knowledge would be plus- Familiarity with Verilog/VHDL - Tcl, Perl, Python scripting - Strong verbal and written communication skills

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