ASIC RTL & CPU Design Engineer 5 To 20 Years

About the Opportunity

5 to 18 years

Open Tracks & Experience Levels

1. Staff CPU Design Engineer (5-8 Years | Bengaluru / Hyderabad | NP: 030 Days):

   Focuses on high-performance in-order or out-of-order CPU core pipeline blocks, micro-architectural research, and PPA optimization.

2. ASIC RTL Design Engineer (6-10 Years | Bengaluru / Hyderabad | NP: up to 60 Days):

   Focuses on IP block and subsystem RTL design, AMBA interconnects, IP integration, and quality sign-off.

3. ASIC RTL Design Engineer Power Management / PMBus (10-15 Years | Hyderabad Only | NP: up to 60 Days):

   Focuses on digital RTL for power management functions, PMBus/SMBus/I2C interfaces, rail sequencing, telemetry, and digital-to-analog boundary interfaces.

4. Senior / Lead ASIC RTL Design Engineer (15-18 Years | Bengaluru / Hyderabad | NP: up to 60 Days):

   Technical ownership across complex subsystems or full designs, architecture decisions, timing closure strategy, quality sign-off gates, and mentoring.

Key Responsibilities

• Micro-Architecture & RTL Ownership:

  Develop and own micro-architecture specifications and write synthesis-friendly RTL in Verilog/SystemVerilog/VHDL for complex IP blocks, subsystems, or critical CPU core blocks (data/control paths, FSMs, register maps).

• Specialty Domain Execution:

• For CPU Design Track: Drive micro-architecture for in-order/out-of-order CPU pipelines (Fetch, Decode, Branch Prediction, Register Renaming, ROB, Load/Store, Cache/Memory subsystems) and collaborate with modeling teams to meet Power, Performance, Area, and Timing (PPAT) targets.
• For PMBus / Power Management Track: Design and own RTL for PMBus/SMBus interface blocks (address handling, packet error checking, command decode, register maps) and digital control for rail sequencing, telemetry reporting, fault detection, and analog/mixed-signal boundary signaling.
• For Senior / Subsystem Track: Partition complex subsystems, define interfaces, drive multiple designs through tapeout, guide mid-level engineers, and serve as the technical point of contact.

• Design Quality & Sign-Off:

  Run, enforce, and close design quality checks including Lint, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), and DFT-aware coding rules.

• Synthesis & Timing Closure:

  Define SDC timing constraints, support logic synthesis, and collaborate with physical design/backend teams to resolve critical timing paths and area/power trade-offs.

• Cross-Functional Collaboration:

  Partner with Architecture, Verification (test plan review, assertions, failure debug, protocol compliance), DFT, Analog/Mixed-Signal, and Post-Silicon Validation teams through silicon bring-up.

Required Qualifications & Technical Skills

• Education:

  B.E. / B.Tech / M.E. / M.Tech in Electronics, Electrical, Electronics & Communication (ECE), Computer Engineering, VLSI Design, or a related discipline.

• Core RTL Expertise:

  5 to 18 years of hands-on front-end ASIC RTL design experience using SystemVerilog, Verilog, or VHDL, with complete ownership of blocks or subsystems from specification to RTL sign-off.

• Protocols & Bus Architectures:

• SoC / Subsystem Roles: Strong command of AMBA interconnects (AXI, AHB, APB) and high-speed/standard interface protocols (PCIe, Ethernet, DDR, NoC, RISC-V/ARM integration).
• Power Management Roles: Hands-on implementation of PMBus, SMBus, or I2C-derived interface logic and power management silicon concepts.
• CPU Design Roles: Deep understanding of microprocessor architecture, pipeline stages, out-of-order execution, integer/floating-point execution, and cache coherency / memory consistency.

• Sign-Off & Implementation:

  Proven expertise in Lint, CDC, RDC analysis, logic synthesis, Static Timing Analysis (STA), and SDC constraint development.

• EDA Tools & Scripting:

  Proficiency with industry-standard tools such as Synopsys Design Compiler, SpyGlass / VC-SpyGlass, VCS, Cadence Xcelium, Mentor QuestaSim, Verdi, and scripting in Python, Perl, or TCL.

Good to Have (Role Dependent)

• Low-power design techniques using UPF (power domains, clock/power gating, retention, isolation).
• Formal verification experience using JasperGold (FPV) and SystemVerilog Assertions (SVA).
• Exposure to AVSBus, Power Management ICs (PMIC), analog mixed-signal boundaries, or automotive/industrial functional safety standards.
• FPGA prototyping or post-silicon bring-up exposure