ASIC RTL Architect

Greetings from Wipro

ASIC RTL Architect

Role Details

Requirement Name : ASIC RTL Architect

Experience:15 Years +

Work location : Bengaluru / Hyderabad / Kochi / Chennai / Any Location

Work Mode : Hybrid

Job Type: Full-Time with Wipro

JD

What You Bring:

• 15+ years in RTL design and integration, with multiple tape-outs in a lead or architect role.
• Expert Verilog / SystemVerilog and strong micro-architecture skills.
• Deep experience with AMBA (AXI/AHB/APB), NoC and high-speed interfaces such as PCIe, DDR/LPDDR, Ethernet, USB.
• Solid grasp of low-power design (UPF), clocking, CDC/RDC and timing-driven RTL.
• Proficiency with front-end tools: lint, CDC, synthesis, STA; scripting in Python, Perl or Tcl.
• Clear technical communication with customers and cross-functional teams.

What You Will Do:

• Define micro-architecture, block partitioning and interface specifications from system requirements.
• Own PPA trade-offs and RTL quality: lint, CDC/RDC, synthesis and constraints (SDC, UPF).
• Lead subsystem and SoC integration, and drive design and code reviews.
• Partner with DV, DFT and PD to close verification, testability, timing and power.
• Mentor and technically guide RTL teams; act as the escalation point for design issues.
• Support emulation, FPGA prototyping, silicon bring-up and root-cause analysis.

Good to Have :

• ARM or RISC-V subsystem integration
• Die-to-die / UCIe and chiplet architectures
• Post-silicon debug experience