AjnaTech Services

Job Description: You will be responsible for performing ASIC/IP/Sub-System/SoC level design verification for high-speed interfaces, ensuring functional correctness across PCIE and other protocols under PVT conditions. Your role will involve developing and executing test plans using SystemVerilog and UVM, as well as collaborating with cross-functional teams for design bring-up, debug, and coverage closure. Key Responsibilities: - Perform ASIC/IP/Sub-System/SoC level design verification for high-speed interfaces - Ensure functional correctness across PCIE and other protocols under PVT conditions - Develop and execute test plans using SystemVerilog and UVM - Collaborate with cross-functional teams for design bring-up, debug, and coverage closure Qualification Required: - Proven experience in verifying complex IPs, subsystems, or SoCs - Strong expertise in SystemVerilog and UVM methodology - Hands-on knowledge of object-oriented programming and scripting (Python, Perl) - Familiarity with PC system architecture: PCI Express, USB, Ethernet, HyperTransport, DDR,