Semiconductor Design Engineer 3

Job Description

Need 5 to 10 years of relevant work experience - Requires hands-on experience in developing and understanding building block schematics, memory schematics, and running circuit simulation with spice simulators - Experience in deciphering circuit behavior from schematics - Ability to develop and maintain test benches and test vectors using simulation tools - Familiarity with circuit characterization, timing libraries, timing arcs - Experience in Verilog MOS switch level models and netlist simulation - Knowledge in static timing analysis - Experience in Gate level simulations with SDF back annotation - Ability to debug SDF annotation issues and ensure good coverage - Experience with latch based designs and their timing requirements - Capacity to debug gate level simulation failures and root cause the failures in actual circuits - Hands-on knowledge of System Verilog Assertions to specify expected design behavior - Familiarity with UVM is a plus - Strong communication skills required - Skill in gate level simulation, spice correlation, debugging failures and providing fixes at gate or transistor level - Experience in IP and SoC Verification, particularly with memory or full chip Verification - Proficiency in System Verilog, UVM (Universal Verification Methodology) - Experience in Verification Environment: Testbench Development, debugging and closure of functional coverage - Ability in Gate Level Simulations and Debugging - Knowledge in Python and automation - Familiarity with Static timing analysis (STA) is a plus.