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Cadence Design Systems logo

Principal Product Validation Engineer

6 - 11 years

6 - 12 Lacs

Noida, Uttar Pradesh, India

Posted:2 weeks ago| Platform: Foundit logo

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Skills Required

omputer science Process Automation VHDL Simulation

Work Mode

On-site

Job Type

Full Time

Job Description

The person should be an Electrical, Electronics or Computer Science Engineer with very good understanding of HDLs (Verilog and/ or VHDL). Prior experience in simulation/emulation using these languages. He/ she should have a good working knowledge of EDA tools (Cadence/ Others) with focus towards debugging design/ verification problems using these tools. Experience in process automation with scripting. Experience with SystemVerilog, C++, UVM. Experience with Functional Verification of complex digital systems, e.g. SoC Verification, with a Hardware Verification Language (HVL) like SystemVerilog. Experience designing and implementing complex functional verification environments is required. Knowledge of protocols like PCIe, USB3/4, DP an added advantage.

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