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Lead Hardware Engineer

Lead Hardware Engineer

Cadence

4 - 9 years

20 - 25 Lacs

Bengaluru

Posted:6 days ago| Platform:

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Skills Required

Design verification static timing analysis SOC Routing Perl Logic design Floor planning RTL Python Physical design

Work Mode

Work from Office

Job Type

Full Time

Job Description

Expertise in logic synthesis, conformal, static timing analysis and Place and Route (PnR) Hands on experience in all aspects of the chip development process Experience in creating or improving low power synthesis methodologies Experience with scripting languages like Perl, Tcl or Python Floorplan, Place and Route at block level, physical design verification, LVS, DRC, IR drop analysis; netlist to gds at block level RTL logic design or implementation experience on multi-million gate ASICs will be a plus Strong communication skills to effectively communicate across all internal groups Description: As a synthesis, PnR Engineer, you will have responsibilities spanning various aspects of SOC design and implementation. Responsible for activities like Synthesis, LEC, Conformal, P&R etc. You will be working closely on methodology for improving synthesis QOR. Responsible for floor planning, placement and routing at block level. Will need to work closely with other engineers that are members of the RTL, STA and Physical Design teams. Education & Experience: BS or MS in EE, EECS, or CS is required 4+ years relevant work experience

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Cadence

www.cadence.com

Software, Electronic Design Automation

San Jose

Approx. 8,000 Employees

176 Jobs

Key People

Anirudh Devgan

President and CEO
Tom Beckley

Senior Vice President
John Wall

Senior Vice President of Marketing
Jason Huang

Senior Vice President

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