92 Virtuoso Jobs - Page 4

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Requirements: Strong layout knowledge with a minimum of 6 to 10 years of experience Applicants must hold a Bachelors degree Skills include Cadence layout, Cadence schematic capture, using CALIBRE Hercules verification tools. Strong layout knowledge in submicron process, e.g. 16nm, 7nm, 5nm, 3nm etc Experienced in digital (standard cell, memory, I/O) layout Experienced in analog layout is also a plus Job Description: Responsible to understand and apply ...

You will be involved in the design and development of high speed interface / high speed serial links (HSL) circuits upto 10 Gbps, PCIe Gen4, USB 3.1 Gen2/Gen1, MPHY, MIPI, IOs & LVDS. You will be responsible for PLLs/DPLLs/ADC design. Knowledge of analog circuit design and intuition is important. You should be able to coordinate the circuit design teams and the logic design teams. Ability to lead a team and work towards product delivery. Experience of Layout and IC fabrication will be preferable. Knowledge of SerDesis preferable. Excellent verbal and written communication skills. Working knowledge in the technology nodes of 65, 45, 28nm is preferred. The job function demands for the deep und...

Min 4 Years of overall experience in ASIC Verification Should have worked on AMS Verification for minimum of 2 years Develop and execute verification plans for AMS designs. Cadence Virtuoso, Spectre, or AMS Designer.

Responsibilities: * Ensure physical verification with Caliber and LVS tools * Collaborate on layout planning and execution using Virtuoso software * Perform DRC checks for design compliance Annual bonus

Responsibilities: * Create detailed layout designs using Virtuoso software. * Perform physical verification through DRC, LVS, ESD checks. * Collaborate with cross-functional teams on floor planning and antenna integration. Annual bonus

Job Description Potential candidate has to efficiently executes business strategies that are in line with organisational objectives. He/She also coordinates with channel partners to identify regional market opportunities, and builds working relationships amongst a diverse range of customers. Must have experience in field of sales and marketing of Fa ade systems. Experience of specifying products and handling projects with big customers / Builders / consultants and Architects. Potential candidate must have proven record of preparing and executing a Business plan in similar capacity to achieve desired target. Must have knowledge of Development cycle of a Fa ade system. Technically sound about ...

About the Role: We are seeking a highly skilled and experienced Analog Layout Manager to lead our layout engineering team in the development of cutting-edge analog and mixed-signal ICs. This role requires deep technical expertise in analog layout, strong leadership capabilities, and the ability to deliver high-quality silicon in aggressive timelines. Key Responsibilities: Lead and manage a team of analog layout engineers to deliver high-quality layouts for analog and mixed-signal IPs (e.g., ADCs, DACs, PLLs, LDOs, PMICs, etc.) Own the floor planning, partitioning, and layout strategy for complex blocks and full chip integration. Collaborate closely with circuit design, verification, and phys...

• Drive Area estimation, Floor Planning, Placement, Routing, Power planning, Verification, EMIR, ESD-LUP Verification & Tape out. • Understanding of low parasitic, high frequency design techniques. • Finfet process & Lower nodes; 2nm/3nm/5nm/7nm Required Candidate profile • Exp with Cadence (Virtuoso), Synopsys (CC), Calibre & ICV verification tools like LVS, DRC, Extraction. • Debugging/fixing LVS/DRC errors • Experience with EMIR, PERC tools. • Skill/TCL scripting.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. JD for CIC Frontend req AE3 Your role will be to meet customers/prospects and identify & qualify the opportunities, work out agreeable and achievable evaluation criteria, run through the evaluation and convert the opportunities into business leading to deployment of an efficient circuit simulation and mixed signal methodology using Cadence tools. It requires a very good understanding of customer flow & challenges and a good analytical ability to resolve issues impacting production schedule. Hands-on knowledge / experience on analog and mixed-signal circuit Design / Debug / modeling a...

Experience in memory layout. Memory Leafcell layout library design from scratch, including top-level integration. Knowledge of different types of memory architectures. Proficient in DRC, LVS, ERC, boundary conditions. Contact at Shubhanshi@incise.in Required Candidate profile 3-8 years of experience in Memory/Custom Layout design. Cadence Virtuoso layout editor and Calibre physical verification flow

Layout concepts: Good knowledge in layout matching techniques and it usage Able to do floorplan, placement , routing and lvs-drc clean at block level Hands on experience in OPAMP , LDO, BGA and reference generate blocks Handle the block independently and able to communicate with design team Expertise in EM and IR fixes Good knowledge in floor planning of IPs like RX, TX and Synth IPs Understanding of DRC errors and fixing it including density errors . Good knowledge in Tsmc 6nm technology node Interested candidates can share their resumes to shubhanshi@incise.in

www.Sevyamultimedia.com Layout Lead About Us We are a technology consulting company delivering best-in class Chip Design Services. Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow. With over 40+ tapeouts and expertise spanning the breadth of chip design, we offer a wide variety of Semiconductor skills Approach We support a mix of engagement models to support diverse client requirements. Engagement Models Turnkey (SoW) Engagement Staff Augmentation (T&M) Offshore Design Center Key Enablers Hands on Leadership Proven Industry Experts TSMC DCA Parternship Collaboration with Academia Message About the job Analog Layout Design Lead with 7+ years...

www.Sevyamultimedia.com Layout Senior Manager/ Manager About Us We are a technology consulting company delivering best-in class Chip Design Services. Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow. With over 40+ tapeouts and expertise spanning the breadth of chip design, we offer a wide variety of Semiconductor skills Analog IP Design Foundation - OpAmp, Bandgap IOs - GPIO, I2C, LVDS Clocking - PLL Power - LDO PDK, Design Automation DRC/LVS/Extraction Rule deck Development PCell Development Automation Tools in Perl, Python, GoLang Approach We support a mix of engagement models to support diverse client requirements. Engagement Models Turn...

www.Sevyamultimedia.com Layout Lead About Us We are a technology consulting company delivering best-in class Chip Design Services. Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow. With over 40+ tapeouts and expertise spanning the breadth of chip design, we offer a wide variety of Semiconductor skills Approach We support a mix of engagement models to support diverse client requirements. Engagement Models Turnkey (SoW) Engagement Staff Augmentation (T&M) Offshore Design Center Key Enablers Hands on Leadership Proven Industry Experts TSMC DCA Parternship Collaboration with Academia Message About the job Analog Layout Design engineer with 3-7+...

We are seeking a skilled QA Engineer with strong experience in Salesforce (SFDC) migration testing. The ideal candidate will have expertise in testing automation and manual testing with a focus on data integrity, security, and API functionality. The role requires close collaboration with cross-functional teams including business stakeholders and project managers to ensure successful project delivery. Key Responsibilities: Conduct migration testing with a focus on Salesforce (SFDC) platforms. Perform automation testing using tools such as Virtuoso. Validate data integrity during and after migrations, ensuring accuracy and consistency. Perform API testing to validate data exchange between syst...

Perform Salesforce (SFDC) migration & data integrity testing Execute automated tests , Virtuoso Conduct API testing & validate system integrations test plans, cases, & reports Create & manage detailed test plans, cases, and report.

Role & responsibilities 1.Job description - Analog Layout: Exciting Opportunity for Analog Layout Engineers ! Elevate your career with Digicomm Semiconductor Private Limited and take the next leap in your professional journey. Join us for unparalleled growth and development. Responsibilities:- Excellent work experience in Analog / Mixed Signal Layout design in advanced FinFET processes like 16nm, 12nm, 10nm, 7nm, 5nm, 3nm Expertise on complete PNR flow CTS,routing, Timing Closure. Hands on experience in any or multiple critical blocks such as SERDES, PHY, HDMI, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc. Excellent underst...