Technical Lead

Job Summary:

We are looking for a seasoned FPGA Developer to lead the migration of existing FPGA/CPLD code to new chipsets. This role involves understanding of existing VHDL code based on EoL FPGA and migrate it to another active FPGA, and toolchain selection, pin mapping, schematic review, and potentially contributing/review to hardware design.

Key Responsibilities:

• Lead the migration of legacy FPGA/CPLD code to new chipsets. (existing source code is available )
• Evaluate and select appropriate FPGA/CPLD chipsets and development toolchains.
• Define pin mapping and ensure seamless integration with hardware platforms.
• Collaborate with hardware teams to review and validate schematic designs.
• Document design specifications, migration strategies, and validation procedures.
• (Preferred) Contribute to hardware design for schematic review

Required Skills:

• Experience of implementation of Profibus Protocol is a big plus

• Minimum 8 years of experience in

  FPGA/CPLD development

  .

• Proficiency in VHDL, Verilog

• Hands-on experience with

  FPGA toolchains

  (e.g., Xilinx Vivado, Lattice).
• Strong

  understanding of pin mapping, timing constraints, and schematic design.

• Familiarity with hardware design tools (e.g., Altium Designer) is a plus.
• Team collaboration working closely with hardware, software, and QA teams.
• (Preferred)

  some C exposure for UART/USB driver inside VHDL code of CPLD.

Chipsets involved:

FPGA: XC3S1000-4FT256C : EoL

CPLD: XC2C64A-5VQ100C : EoL

FPGA: XC3S50AN-4TQG144I: active