This role is for one of the Weekday's clients
Min Experience: 7 yearsJobType: full-timeAs a
Standard Cell Layout Engineer
, you will be responsible for the layout design and optimization of standard cells, analog, and custom blocks used in high-performance integrated circuits. You will work closely with circuit designers, verification engineers, and process technology teams to ensure design accuracy, manufacturability, and adherence to technology constraints. The role requires a strong understanding of CMOS design principles, parasitic extraction, layout-versus-schematic (LVS) and design rule checks (DRC), and layout methodologies across multiple technology nodes. You will contribute to improving layout automation, design efficiency, and quality standards while maintaining tight control over physical and electrical design aspects.
Requirements
Key Responsibilities
- Design and implement standard cell layouts, ensuring high performance, minimal power consumption, and optimal area utilization
- Develop custom and analog layouts for critical design blocks, following process design rules and project specifications
- Collaborate with circuit design engineers to translate schematics into layout with optimal device matching and routing efficiency
- Perform layout verification including LVS, DRC, ERC, and parasitic extraction (PEX) checks, ensuring first-time-right design quality
- Optimize layout structures for performance, yield, and manufacturability, addressing design feedback promptly
- Participate in layout reviews and contribute to continuous improvements in layout design methodologies and automation scripts
- Ensure compliance with foundry process technologies and fabrication constraints across technology nodes (e.g., 7nm, 5nm, 3nm)
- Work closely with the physical design and PDK teams to align design rules and resolve layout-related challenges
- Support tape-out activities by preparing final layout data, resolving verification issues, and ensuring sign-off readiness
- Document layout design guidelines, best practices, and workflows for internal design process improvement
What Makes You a Great Fit
- Experience: Minimum 7 years of proven experience in standard cell layout, custom layout, and analog layout design
- Technical Proficiency: Deep understanding of CMOS device physics, transistor-level layout, and analog circuit layout principles
- Tools Expertise: Proficiency in layout tools such as Cadence Virtuoso, Mentor Graphics, or Synopsys Custom Compiler
- Verification Skills: Strong hands-on experience in LVS/DRC verification, parasitic extraction (PEX), and physical verification flows
- Process Knowledge: Familiarity with advanced process technologies (FinFET, SOI, CMOS) and foundry design rules
- Attention to Detail: High level of precision and focus on layout symmetry, matching, and parasitic minimization
- Collaboration: Excellent communication and teamwork skills to work effectively with cross-functional design and verification teams
- Analytical Thinking: Strong problem-solving and debugging skills, with the ability to anticipate and address design challenges proactively
- Continuous Learning: Enthusiasm for staying updated on emerging layout technologies, EDA tools, and semiconductor trends
- Quality Focus: Commitment to delivering layouts with high accuracy, manufacturability, and performance efficiency
