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Analog Devices
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Staff Engineer, Physical Design Engineering

Staff Engineer, Physical Design Engineering

Analog Devices

9 - 12 years

14 - 19 Lacs

bengaluru

Posted:1 day ago| Platform:

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Skills Required

automation semiconductor dft analog signal processing healthcare perl signal integrity physical design python

Work Mode

Work from Office

Job Type

Full Time

Job Description

Analog Devices Digital Business Unit (DBU) is seeking a Staff STA Engineer to lead timing sign-off and closure for complex mixed-signal SoCs manufactured on advanced process nodes and operating at high-speed clock rates. These SoCs integrate multiple processor cores and high-performance signal processing hardware. The role ensures that designs meet timing, signal integrity, and reliability requirements through advanced analysis and optimization techniques.

Key Responsibilities

Perform full-chip and block-level STA for multiple modes and corners.
Analyze and resolve setup, hold, and clock domain crossing (CDC) issues.
Create and validate timing constraints (SDC) for synthesis and P&R flows.
Execute timing sign-off using industry-standard tools (eg, PrimeTime, Tempus).
Implement ECOs for timing fixes and validate changes.
Collaborate with RTL, physical design, and DFT teams to ensure timing requirements are met.
Develop automation scripts (TCL, Python, Perl) to streamline STA tasks and improve efficiency.
Address challenges related to OCV, AOCV, POCV , and multi-voltage domains.

Position Requirements

Education : B.Tech/M.Tech in Electrical/Electronics Engineering.
Experience : 9-12 years in STA and physical design implementation for high-speed SoCs on advanced nodes (28nm, 22nm, 16nm, 10nm, 5nm).
Strong expertise in Static Timing Analysis , constraint development, and sign-off.
Ability to innovate flows to meet QoR targets and ensure predictability.
Good understanding of device/interconnect and circuit aspects of UDSM technologies.
Proficiency in TCL, Python , or other scripting languages.
Excellent communication skills and ability to work in a cross-functional global team .
Experience with low-power design techniques (UPF/CPF).
Familiarity with signal integrity and power integrity analysis .
Knowledge of advanced process nodes and variation modeling .

#LI-SM1

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Staff Engineer, Physical Design Engineering