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Analog Devices
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Staff Engineer, Physical Design Engineering

Staff Engineer, Physical Design Engineering

Analog Devices

9 - 12 years

14 - 19 Lacs

bengaluru

Posted:1 day ago| Platform:

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Skills Required

asic semiconductor dft analog cad packaging healthcare perl physical design python

Work Mode

Work from Office

Job Type

Full Time

Job Description

Analog Devices Digital Business Unit (DBU) is seeking a Senior Physical Design Engineer to lead the development of complex mixed-signal SoCs manufactured on leading-edge process nodes and operating at high-speed clock rates. These SoCs integrate multiple processor cores and high-performance signal processing hardware. The role involves end-to-end physical implementation of ASIC/SoC designs, ensuring optimal performance, power, and area (PPA) while meeting timing and manufacturability requirements.

Key Responsibilities

Execute RTL-to-GDSII flow including synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, and optimization.
Perform Static Timing Analysis (STA) , power integrity checks, signal integrity (SI), and electromigration (EM) analysis.
Optimize PPA metrics through congestion analysis, routing strategies, and library utilization.
Ensure DRC/LVS compliance , run physical verification, and manage ECOs for design revisions.
Collaborate with RTL, DFT, packaging, and backend teams for seamless integration.
Customize design flows, automate processes using TCL, Python, Perl , and contribute to CAD development.
Implement designs on advanced process technologies (eg, 22nm, 16nm, 5nm, 3nm).
Mentor junior engineers and contribute to methodology improvements .
Experience with low-power design techniques (UPF/CPF).

Position Requirements

Education : B.Tech/M.Tech in Electrical/Electronics Engineering.
Experience : 9-12 years in physical design implementation of complex high-speed SoCs on advanced nodes (28nm, 22nm, 16nm, 10nm, 5nm).
Expertise in floorplanning, power planning, placement & routing, clock planning, CTS, and parasitic extraction .
Strong knowledge of Static Timing Analysis , constraint development, and sign-off.
Ability to innovate flows to meet QoR targets and ensure predictability.
Good understanding of device/interconnect and circuit aspects of UDSM technologies.
Proficiency in TCL, Python , or other scripting languages.
Excellent communication skills and ability to work in a cross-functional global team .

#LI-SM1

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Staff Engineer, Physical Design Engineering