Senior PLL Design Engineer

As a Senior PLL Design Engineer/Lead/Architect at Eximietas, your role will involve architecting, designing, and developing LC PLL Circuits. You will be expected to have a strong understanding and knowledge of clocking circuits, CDR, and SERDES designs. Additionally, hands-on experience in high-speed circuits for 32G, 64G, and higher is essential. Previous working experience in Samsung PDK lower technology nodes will be considered as an advantage. **Qualifications:** - Bachelors or Masters degree in Electronics, Electrical, Telecom, or VLSI Engineering. - Minimum 7+ years of experience in PLL Design. If you are passionate about pushing the boundaries in PLL design and have a proven track record in the field, we encourage you to apply by sharing your resume at maruthiprasad.e@eximietas.design. Referrals for suitable candidates are highly appreciated. (Note: No additional details about the company were provided in the job description.),