Senior Physical Design Engineer

ROLE & RESPONSIBILITIES
Engineer will be responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, Antenna fixing &signal integrity, Power grid analysis atc in ASIC PNR FlowEngineer will be responsible for executing the block level place and route assignments from Netlist through GDS flowShould be able to do full chip implementation of complex SoCs (RTL-to-GDSII), but it is not must.To close STA timing across all corners and modes for blocks and should be able to generate ECO independently.Will be responsible to Work with design teams for closing CTS, IO timing, DFT timing.Responsible for digital design automation, flow-automation and regression across RTL-to-GDSII.To ensure successful delivery of his block(s) to customersESSENTIAL SKILLS & EXPERIENCEMinimum Experience required is 5 Years in Physical DesignStrong fundamentals on Physical design including Floorplan, power grid analysis, placement, cts, routing, DRC-LVS closure, timing closure, antenna fixing, signal integrity on 65nm, 45nm, 28nm, 16nm geometry.Sound expertise in Tcl, Perl, Shell scripting. Technically sound & good team playerHands-on experience with Place and Route tools (Synopsys - ICC, Cadence – Innovus / Encounter) is a must.Experience on latest technology (28nm,16nm,7 nm)EDUCATION BACKGROUNDB.E./ B.S./ B.Tech/ M.S./ M.Tech in VLSI/Electronics/Electrical/Computer/Instrumentation Engineering.