Job Description

Are you a Physical Design Engineer looking to make a significant impact in the semiconductor industry? Join our team and be a part of cutting-edge ASIC Implementation and chip design! Key Responsibilities: Drive ASIC Implementation, from Synthesis to Place & Route. Manage DFT, Timing Closure, and Power Optimization. Perform DRC/LVS/PERC/ERC analysis for Physical Verification. Collaborate with international teams to optimize IP and push boundaries in Physical Design. Required Skills: 3+ years of experience in ASIC Implementation and Timing Closure. Expertise in Synthesis, DFT, Floorplan, Place & Route. Proficiency in scripting languages: Tcl, Perl, Python, Make. Strong communication and problem-solving skills. Bonus Skills: Experience with low-power design techniques. Knowledge of ARM-based SoCs. Hands-on experience with Verilog RTL design.