MTS Silicon Design Engineer

Job Description

Job Title: Member of Technical Staff (MTS) DFT Verification Experience: 6+ years Location: Bangalore Job Description: We are seeking a dedicated and experienced Member of Technical Staff (MTS) specializing in DFT Insertion and Verification . The candidate will play a key role in ensuring the robustness and reliability of Tile and SoC designs by implementing and verifying advanced test architectures. Key Responsibilities: Perform SMS (Structural Mode Scan) Insertion and verification at both Tile and SoC levels. Design and verify Memory BIST (Built-In Self-Test) architectures, including initialization and integration. Implement and validate memory repair strategies, including fuse programming (eFuse) and redundancy management. Debug and optimize DFT flows to meet high fault coverage and manufacturability standards. Collaborate with cross-functional teams to ensure seamless DFT integration across various design phases. Analyze test results, resolve silicon and test-related issues, and contribute to yield improvements. Required Skills: Expertise in SMS Insertion and verification for Tile and SoC level designs. Proficiency in Memory BIST architecture, including repair mechanisms and eFuse configuration. Hands-on experience with DFT tools like Mentor Tessent, Synopsys DFT Compiler, or Cadence Modus. Strong scripting skills in Python, Perl, or TCL for automation of test flows. Knowledge of RTL design and debugging (Verilog/VHDL). Excellent problem-solving and analytical skills, especially in debugging silicon failures. Preferred Qualifications: Experience with low-power DFT methodologies and advanced compression techniques. Familiarity with industry standards for JTAG and boundary scan. Hands-on experience with post-silicon validation, bring-up, and characterization.