Job Description

Develop and optimize voltage scaling and isolation strategies across multiple power domains. Work with the physical design and RTL teams to ensure voltage islands and isolation cells meet design specifications. Create and maintain Unified Power Format (UPF) files to define power intent across the design. Ensure proper definition of power domains, retention, and power shutoff requirements to meet power integrity. Collaborate with the verification team to implement power-aware verification strategies using UPF, ensuring all power-related checks are met. Perform power analysis to identify potential issues and optimize the design. Work closely with the architecture, RTL, DFT, and physical design teams to integrate power management requirements, ensure alignment on power specifications, and resolve power-related issues. Document power management strategies, UPF implementation details, and analysis findings. Present findings and recommendations to design and management teams. Provide guidance and training to junior engineers and cross-functional teams on DFP, VSI, and UPF best practices and methodologies. PREFERRED EXPERIENCE: Expertise in UPF power intent formats and power-aware verification flows. Strong knowledge of DFP techniques, including power gating, multi-voltage, clock gating, and DVFS. Experience with VSI, power domain partitioning, and isolation cell management. Strong problem-solving, analytical, and communication skills. Ability to collaborate effectively across multiple teams and manage complex design requirements. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering.