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Posted:2 months ago| Platform: 
Work from Office
Full Time
Proficient in RTL design using Verilog/SystemVerilog or VHDL In-depth knowledge of FPGA architecture and development flows (synthesis, P&R, timing analysis) Familiarity with high-speed interfaces and protocols like PCIe, Ethernet, DDR, AXI, AHB, SPI Required Candidate profile Experience with debugging tools like ChipScope, SignalTap, Logic Analyzer Proficiency in scripting languages like Python, Tcl, or Perl for automation of FPGA workflows
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