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Design & write robust verification environments (testbenches) to achieve high code coverage Utilize simulation tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS) to verify RTL functionality 5+ years of exp in design verification for ASICs or SoCs Required Candidate profile Debug and analyze verification failures to identify the root cause of design issues Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM) scripting -Python, Perl
5yrs Exp in working on IP/Subsystem/SocVerification expert in Protocol on Flash Storage device Controller with unipro and MIPI PHY& Working on any of cross functional flows like Reset, Ras(Error &Interrupt), Security, low Power for Highspeed IO IPs Required Candidate profile Good Skills in System Verilog, shell programming/scripting (e.g. Tcl, Perl, Python etc.) Experienced in one or more of various verification methodologies – UVM, formal and low power , Emulation/FPGA
Dear Candidate, We are conducting week end F2F drive on 30th Aug 25 for SD -WAN Skill. Location: Noida, Bangalore, Hyderabad, Chennai Experience : 7+ years. Mode : F2F interview on 30th Aug 25. Thanks Ramesh. A Rameshg@eresourcetech.com
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